Infrastructure-grade integrated voltage controlled oscillator (VCO) with linear tuning characteristics and low phase noise

• US 9,503,017 B1
• Filed: 09/28/2010
• Issued: 11/22/2016
• Est. Priority Date: 09/29/2009
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Easter, Jacob K., Roberts, William Thales, Jin, Li, Farahvash, Shayan, Stegmeir, David Conrad
• Primary Examiner(s): Gannon, Levi
• Application Number:
  US12/892,049
• Time in Patent Office: 2,247 Days
• Field of Search: 331/34, 331/36.C, 331/117.FE, 331/117.R, 331/167, 331/177.V
• US Class Current: 1/1
• CPC Class Codes: H03B 2200/005 including measures to switch a capacitor
• CPC Class Codes: H03B 2201/011 the means being an element with a variable capacitance
• CPC Class Codes: H03B 5/1206 using multiple transistors for amplification
• CPC Class Codes: H03B 5/1243 the means comprising voltage variable capacitance diodes
• CPC Class Codes: H03B 5/1265 switched capacitors

Abstract

The described devices, systems and methods include a voltage controlled oscillator. The voltage controlled oscillator includes a fine-tuning varactor network, a switch capacitor array having a first plurality of binary capacitor array elements and a second plurality of thermometer code capacitor array elements, and a tank inductor network including a first inductor in parallel with a second inductor.

Claims

1. A capacitor array comprising:

a capacitor array element including an NFET switch coupled to a capacitor to form a first node;

a DC pedestal and a voltage swing reduction circuit comprising;

a first filter having a first filter input and a first filter output, the first filter input coupled to the first node;

a second filter having a second filter input and a second filter output;

a transmission gate coupled to the first filter output and the second filter input;

a pedestal switch coupled to the second filter output; and

wherein the transmission gate and the pedestal switch are configured to be on when the NFET switch is off.

2. The capacitor array of claim 1 wherein the pedestal switch further includes a FET transistor, a first resistor coupled between a drain of the transistor and a supply voltage, and a second resistor coupled between a source of the transistor and ground.

3. The capacitor array of claim 1 wherein the first filter is a single pole resistor-capacitor filter, and the second filter is a single pole resistor-capacitor filter.

4. The capacitor array of claim 1 wherein the transmission gate comprises a first PFET transistor coupled in parallel with a first NFET transistor.

5. The capacitor array of claim 1 wherein the capacitor in the capacitor array element is coupled between a supply voltage and the first node.

6. The capacitor array of claim 1 wherein a drain of the NFET switch is coupled to the first node and a source of the NFET switch is coupled to ground.

7. The capacitor array of claim 6 wherein the transmission gate comprises a first PFET transistor coupled in parallel with a first NFET transistor.

8. The capacitor array of claim 7 wherein a gate of the NFET switch is coupled to a gate of the first PFET transistor and coupled to a gate of the first NFET transistor via an inverter.

9. A capacitor array comprising:

a capacitor coupled between a supply voltage and a first node;

a capacitor switching element coupled between the first node and ground;

a first filter coupled between the first node and a second node;

a transmission gate coupled between the second node and a third node;

a second filter coupled between the third node and a fourth node; and

a pedestal switching element coupled between the fourth node and ground.

10. The capacitor array of claim 9 wherein the transmission gate and the pedestal switching element are operated complementary to the capacitor switching element.