Dynamic error vector magnitude duty cycle correction

• US 9,503,026 B2
• Filed: 09/18/2014
• Issued: 11/22/2016
• Est. Priority Date: 09/19/2013
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Lam, Lui, Doherty, Mark M.
• Primary Examiner(s): NGUYEN, HIEU P
• Application Number:
  US14/490,488
• Publication Number:
  US 20150077187A1
• Time in Patent Office: 796 Days
• Field of Search: 330/285, 330/296, 330/136
• US Class Current: 1/1
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0266 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/111 the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/165 A filter circuit coupled to the input of an amplifier
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/351 Pulse width modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/429 Two or more amplifiers or one amplifier with filters for different frequency bands are coupled in parallel at the input or output
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/555 A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 2203/7209 the gated amplifier being switched from a first band to a second band
• CPC Class Codes: H03F 2203/7221 the gated amplifier being switched on or off by a switch at the output of the amplifier
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H04B 1/04 Circuits

Abstract

Aspects of this disclosure relate to dynamic error vector magnitude (DEVM) compensation. In one embodiment, an apparatus includes an amplifier, a low pass filter, and a bias circuit. The amplifier, such as a power amplifier, can amplify an input signal. The low pass filter, such as an integrator, can generate a correction signal based at least partly on an indication of a duty cycle of the amplifier. The indication of the duty cycle of the amplifier can be an enable signal for the amplifier, for example. The bias circuit can generate a bias signal based at least partly on the correction signal and provide the bias signal to the amplifier to bias the amplifier.

Claims

1. An apparatus comprising:

an amplifier configured to amplify an input signal;

a low pass filter configured to receive an indication of a duty cycle of the amplifier and to generate a correction signal based at least partly on the indication of the duty cycle of the amplifier, the indication of duty cycle being a binary signal having an activated state corresponding to the amplifier being enabled and a deactivated state corresponding to the amplifier being disabled; and

a bias circuit configured to generate a bias signal based at least partly on the correction signal such that changes in the bias signal are inversely proportional to changes in the duty cycle of the amplifier, and the bias circuit configured to bias the amplifier using the bias signal so as to compensate for a variation in gain of the amplifier from thermal effects as the duty cycle of the amplifier changes.

2. The apparatus of claim 1 wherein the bias circuit is configured to receive an enable signal and to selectively pulse an output of the amplifier based at least partly on the enable signal.

3. The apparatus of claim 1 wherein the indication of the duty cycle of the amplifier is an enable signal for the amplifier, the enable signal being a different signal than the input signal.

4. The apparatus of claim 1 wherein the low pass filter is an integrator configured to integrate the indication of the duty cycle of the amplifier.

5. The apparatus of claim 4 wherein the integrator includes a charge pump.

6. The apparatus of claim 1 wherein the low pass filter is an analog circuit.

7. The apparatus of claim 1 wherein the amplifier includes a power amplifier.

8. The apparatus of claim 7 wherein the power amplifier includes a bipolar transistor having a collector configured to provide an amplified version of the input signal and the bias circuit is configured to provide the bias signal to a base of the bipolar transistor.

9. The apparatus of claim 7 wherein the apparatus is a mobile device that includes an antenna configured to transmit a radio frequency signal received from the power amplifier.

10. The apparatus of claim 1 wherein the bias circuit includes a current source configured to generate a correction current based at least partly on the correction signal and the bias circuit is configured to generate the bias signal based at least partly on the correction current.

11. The apparatus of claim 1 wherein the input signal is a radio frequency signal.

12. The apparatus of claim 3 wherein the bias circuit is configured to enable the amplifier to amplify the input signal responsive to the enable signal transitioning from a deactivated state to an activated state, and to disable the amplifier from amplifying the input signal responsive to the enable signal transitioning from the activated state to the deactivated state.

13. An electronically implemented method of biasing an amplifier, the method comprising:

integrating an indication of a duty cycle of the amplifier to generate a dynamic correction signal, the indication of duty cycle being a binary signal;

generating a bias signal based at least partly on the dynamic correction signal such that changes in the bias signal are inversely proportional to changes in the duty cycle of the amplifier; and

biasing the amplifier using the bias signal so as to compensate for a variation in gain of the amplifier from thermal effects as the duty cycle of the amplifier changes.

14. The method of claim 13 further comprising amplifying a radio frequency signal with the amplifier and transmitting the amplified radio frequency signal from an antenna, the amplifier being a power amplifier.

15. A circuit for biasing an amplifier, the circuit comprising:

a duty cycle tracking circuit configured to generate a signal representative of a duty cycle of the amplifier over time based at least partly on a state of an enable signal that enables the amplifier to amplify an input signal and to adjust the signal representative of the duty cycle of the amplifier over time as the duty cycle of the amplifier changes; and

a bias circuit in communication with the duty cycle tracking circuit, the bias circuit configured to generate a bias signal based at least partly on the signal representative of the duty cycle over time such that changes in the bias signal are inversely proportional to changes in the duty cycle of the amplifier and to provide the bias signal to the amplifier to bias the amplifier.

16. The circuit of claim 15 wherein the circuit is configured to control the bias signal such that a gain of the amplifier is substantially constant as the duty cycle of the amplifier changes.

17. The circuit of claim 15 wherein the bias circuit includes a first current source configured to provide a first current when the amplifier is enabled and a second current source configured to provide a second current that is adjustable based at least partly on the signal representative of the duty cycle of the amplifier over time, and the bias circuit is configured to generate the bias based on the first current and the second current.

18. The circuit of claim 15 wherein the duty cycle tracking circuit includes a low pass filter.

19. The circuit of claim 15 wherein the bias circuit is configured to disable the amplifier from amplifying the input signal in response to a transition in the state of the enable signal.