Virtualization of programmable integrated circuits

• US 9,503,093 B2
• Filed: 04/24/2014
• Issued: 11/22/2016
• Est. Priority Date: 04/24/2014
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Karras, Kimon, Blott, Michaela, Vissers, Kornelis A.
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Lin, Aric
• Application Number:
  US14/260,580
• Publication Number:
  US 20150311899A1
• Time in Patent Office: 943 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H03K 19/17724 Structural details of logic blocks
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources

Abstract

A programmable IC includes a plurality of programmable resources, a plurality of shareable logic circuits coupled to the plurality of programmable resources, and a virtualization circuit. The plurality of programmable resources includes programmable logic circuits and programmable routing resources. The virtualization circuit is configured to manage sharing of the plurality of shareable logic circuits between a plurality of user designs implemented in the plurality of programmable resources. The user designs are communicatively isolated from one another on the programmable IC.

Claims

1. A programmable integrated circuit (IC), comprising:

a configuration memory;

a plurality of programmable resources including programmable logic circuits and programmable routing resources, wherein in response to a configuration datastream being loaded into the configuration memory, the programmable resources are configured to concurrently implement two or more different user designs of a plurality of user designs specified in the configuration datastream using respective subsets of the programmable resources;

a plurality of shareable logic circuits coupled to the plurality of programmable resources, wherein the plurality of sharable logic circuits are exclusive from the respective subsets of the programmable resources used to implement the two of more user designs;

a virtualization circuit configured to manage sharing of access to the plurality of shareable logic circuits between the two or more user designs according to a resource allocation policy derived from the configuration datastream; and

wherein the plurality of user designs are communicatively isolated from one another on the programmable IC.

2. The programmable IC of claim 1, wherein:

the sharable logic circuits are hard-wired circuits coupled to the programmable resources on the programmable IC;

the virtualization circuit includes a respective resource manager circuit for each of the shareable logic circuits that is used by the two or more of the plurality of user designs;

each resource manager circuit is configured to;

buffer respective sets of data from the plurality of user designs that use the corresponding shareable logic circuit; and

provide the respective sets of data to the shareable logic circuit according to the resource allocation policy.

3. The programmable IC of claim 2, wherein

the plurality of shareable logic circuits includes at least one hard-wired logic circuit;

the programmable resources are further configured to implement a control circuit configured to set the resource allocation policy of each resource manager circuit.

4. The programmable IC of claim 2, wherein the resource allocation policy indicates at least one of an allocation of bandwidth, address space, or processing time cycles of the shareable logic circuit.

5. The programmable IC of claim 2, wherein:

at least one of the shareable logic circuits is a processor; and

the respective resource manager circuit for the processor includes a hypervisor configured share processing time between ones of the plurality of user designs that use the processor.

6. The programmable IC of claim 2, wherein each of the resource manager circuits is configured to:

perform address translation between respective addresses used by the plurality of user designs for communication with the corresponding shareable logic circuit and an address used by the corresponding shareable logic circuit for communication; and

enforce access to the shareable logic circuit by the plurality of user designs according to the resource allocation policy.

7. The programmable IC of claim 1, wherein the virtualization circuit is configured to manage time sharing of the plurality of programmable resources between at least two of the plurality of user designs via partial reconfiguration.

8. The programmable IC of claim 1, wherein the virtualization circuit is implemented by a subset of the plurality of programmable resources.

9. The programmable IC of claim 1, wherein the virtualization circuit is a hard-wired logic circuit connected to the plurality of programmable resources.

10. The programmable IC of claim 1, wherein the plurality of shareable logic circuits includes a plurality of hard-wired logic circuits.

11. The programmable IC of claim 1, wherein each of the plurality of shareable logic circuits is one of a set of circuits including:

an input/output circuit, a memory, and a processor.

12. The programmable IC of claim 1, wherein at least two of the plurality of user designs are implemented concurrently in the plurality of programmable resources.

13. A method for virtualizing a programmable integrated circuit (IC) for a plurality of user designs, comprising:

identifying a subset of sharable logic circuits, in a set of shareable logic circuits on the programmable IC, that are each used by two or more of the plurality of user designs during operation;

generating a virtualization circuit configured to manage sharing of access to the subset of shareable logic circuits by the two or more of the plurality of user designs according to a resource allocation policy derived from the configuration datastream;

generating a configuration data stream to program a set of programmable resources of the programmable IC to concurrently implement the plurality of user designs and the virtualization circuit;

wherein the two or more of the plurality of user designs are implemented concurrently by respective subsets of the set of programmable resources;

wherein the set of sharable logic circuits are exclusive from the respective subsets of the set of programmable resources; and

wherein the plurality of user designs are communicatively isolated from one another on the programmable IC.

14. The method of claim 13, further comprising:

programming the set of programmable resources using the configuration data stream; and

for each of the shareable logic circuits that is used by two or more of the plurality of user designs, using the virtualization circuit to;

buffer respective sets of data from the plurality of user designs which use the corresponding shareable logic circuit, and

provide the respective sets of data to the shareable logic circuit according to a resource allocation policy; and

wherein the shareable logic circuits include one or more hard-wired logic circuits.

15. The method of claim 14, wherein the resource allocation policy indicates an allocation of bandwidth, address space, or processing time of the shareable logic circuit.

16. The method of claim 14, further comprising:

using, for each of the shareable logic circuits that is used by two or more of the plurality of user designs, the virtualization circuit to perform address translation and enforce access to the corresponding shareable logic circuit according to the resource allocation policy.

17. The method of claim 13, wherein the configuration data stream is configured to implement in the set of programmable resources, at the same time, at least two of the plurality of user designs that both use a same one of the shareable logic circuits.

18. The method of claim 13, further comprising using the virtualization circuit to manage time sharing of the set of programmable resources between at least two of the plurality of user designs via partial reconfiguration.

19. The method of claim 13, further comprising:

programming the programmable IC with the configuration data stream;

receiving an additional set of user designs;

for each of the set of shareable logic circuits on the programmable IC, determining if the shareable logic circuit is used by multiple user designs included in either the plurality of user designs or the additional set of user designs;

generating a second virtualization circuit configured to manage sharing of the shareable logic circuits that are used by two or more of the plurality of user designs; and

generating a second configuration data stream to program a set of programmable resources of the programmable IC to implement the plurality of user designs, the additional set of user designs and the second virtualization circuit.

20. A programmable integrated circuit (IC), comprising:

a plurality of programmable resources, including programmable logic circuits and programmable routing resources, configured and arranged to implement circuits of a plurality of user designs specified by an input configuration datastream;

a plurality of hard-wired logic circuits coupled to the plurality of programmable resources; and

a virtualization circuit configured to manage sharing of the plurality of hard-wired logic circuits between the plurality of user designs implemented concurrently in the plurality of programmable resources according to a resource allocation policy derived from the configuration datastream;

wherein the plurality of user designs are communicatively isolated from one another on the programmable IC.