Circuit for and method of implementing a time-interleaved analog-to-digital converter
First Claim
1. A circuit for implementing a time-interleaved analog-to-digital converter circuit, the circuit comprising:
- a sampling clock generator configured to receive a reference clock signal having a first frequency, the sampling clock generator having a first stage sampling clock generator configured to generate a first plurality of clock signals based upon the reference clock signal and having a second frequency, and a second stage sampling clock generator configured to generate, for each clock signal of the first plurality of clock signals, a second plurality of clock signals having a third frequency;
a first stage having a plurality of switches configured to receive an analog input signal, wherein each switch of the plurality of switches is controlled by a corresponding clock signal of the first plurality of clock signals; and
a second stage having a plurality of analog-to-digital converter banks, each analog-to-digital converter bank having a plurality of analog-to-digital converters and configured to receive the analog input signal by way of a corresponding switch of the plurality of switches; and
wherein each analog-to-digital converter bank of the plurality of analog-to-digital converter banks is configured to receive a plurality of clock phases of a corresponding clock signal of the second plurality of clock signals.
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Accused Products
Abstract
A circuit for implementing a time-interleaved analog-to-digital converter is described. The circuit comprises a sampling clock generator configured to receive a reference clock signal having a first frequency. The sampling clock generator has a first stage sampling clock generator configured to generate a first plurality of clock signals based upon the reference clock signal and having a second frequency, and a second stage sampling clock generator configured to generate, for each clock signal of the first plurality of clock signals, a second plurality of clock signals having a third frequency; a first stage having a plurality of switches configured to receive an analog input signal, wherein each switch of the plurality of switches is controlled by a corresponding clock signal of the first plurality of clock signals; and a second stage having a plurality of analog-to-digital converter banks, each analog-to-digital converter bank having a plurality of analog-to-digital converters and configured to receive the analog input signal by way of a corresponding switch of the plurality of switches.
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Citations
20 Claims
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1. A circuit for implementing a time-interleaved analog-to-digital converter circuit, the circuit comprising:
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a sampling clock generator configured to receive a reference clock signal having a first frequency, the sampling clock generator having a first stage sampling clock generator configured to generate a first plurality of clock signals based upon the reference clock signal and having a second frequency, and a second stage sampling clock generator configured to generate, for each clock signal of the first plurality of clock signals, a second plurality of clock signals having a third frequency; a first stage having a plurality of switches configured to receive an analog input signal, wherein each switch of the plurality of switches is controlled by a corresponding clock signal of the first plurality of clock signals; and a second stage having a plurality of analog-to-digital converter banks, each analog-to-digital converter bank having a plurality of analog-to-digital converters and configured to receive the analog input signal by way of a corresponding switch of the plurality of switches; and wherein each analog-to-digital converter bank of the plurality of analog-to-digital converter banks is configured to receive a plurality of clock phases of a corresponding clock signal of the second plurality of clock signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of implementing a time-interleaved analog-to-digital converter, the method comprising:
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configuring a sampling clock generator to receive a reference clock signal having a first frequency; generating, by the sampling clock generator, a first plurality of clock signals based upon the reference clock signal and having a second frequency; generating, for each clock signal of the first plurality of clock signals, a second plurality of clock signals having a third frequency; receiving an analog input signal at a plurality of switches, wherein each switch of the plurality of switches is controlled by a corresponding clock signal of the first plurality of clock signals; and implementing a plurality of analog-to-digital converter banks, each analog-to-digital converter bank having a plurality of analog-to-digital converters and configured to receive the analog input signal by way of a corresponding switch of the plurality of switches; wherein each analog-to-digital converter bank of the plurality of analog-to-digital converter banks is configured to receive a plurality of clock phases of a corresponding clock signal of the second plurality of clock signals. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification