Efficient calibration of errors in multi-stage analog-to-digital converter
First Claim
1. A multi-stage analog-to-digital converter with digitally assisted calibration, the multi-stage analog-to-digital converter comprising:
- analog-to-digital converter stages in cascade, each analog-to-digital converter stage for generating a respective output code and a respective amplified output residue signal;
wherein for each analog-to-digital converter stage, the multi-stage analog-to-digital converter further comprises;
a dedicated memory element for storing correction terms;
a multiplexer selecting one of the correction terms in the dedicated memory element based on the respective output code; and
circuitry for correcting an error of the multi-stage analog-to-digital converter based on the selected correction term; and
digital circuitry for computing the correction terms in the dedicated memory elements, wherein computing correction terms used for a given analog-to-digital converter stage takes into account an error term from one or more earlier analog-to-digital converter stages.
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Abstract
Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.
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Citations
27 Claims
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1. A multi-stage analog-to-digital converter with digitally assisted calibration, the multi-stage analog-to-digital converter comprising:
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analog-to-digital converter stages in cascade, each analog-to-digital converter stage for generating a respective output code and a respective amplified output residue signal; wherein for each analog-to-digital converter stage, the multi-stage analog-to-digital converter further comprises; a dedicated memory element for storing correction terms; a multiplexer selecting one of the correction terms in the dedicated memory element based on the respective output code; and circuitry for correcting an error of the multi-stage analog-to-digital converter based on the selected correction term; and digital circuitry for computing the correction terms in the dedicated memory elements, wherein computing correction terms used for a given analog-to-digital converter stage takes into account an error term from one or more earlier analog-to-digital converter stages. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A digitally assisted method for calibrating an analog-to-digital converter having multiple stages of analog-to-digital conversion, the method comprising:
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measuring, by dedicated circuitry, one or more characteristics associated with the analog-to-digital converter, wherein the multiple stages generate respective output codes and respective residue signals; computing, by digital circuitry on-chip with the analog-to-digital converter, correction terms to be used for correcting residue signals of the multiple stages based on the measured errors, wherein computing correction terms used for a given stage takes into account a characteristic(s) measured for one or more earlier stages; and writing, by the digital circuitry, the correction terms to separate look up tables provided for each residue signal to be corrected, wherein each look up table is indexed by output codes of a respective stage. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. An apparatus comprising:
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cascaded means having stages for generating respective output codes and respective residue signals; storage means for storing correction terms selectable by a respective output code; means for correcting respective residue signals based on selected correction terms; and means on-chip with the cascaded means for updating correction terms in the storage means based on measured characteristics, wherein updating the correction terms used for a given stage of the cascaded means takes into account the measured characteristics for the given stage of the cascaded means and one or more earlier stage(s) of the cascaded means. - View Dependent Claims (21, 22)
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23. A multi-stage converter with digitally assisted calibration, the multi-stage converter comprising:
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converter stages in cascade; one or more memory elements for storing correction terms; circuitry for adjusting a particular converter stage based on a selected correction term; and digital circuitry for computing the correction terms in the one or more memory elements, wherein computing correction terms used for a given converter stage takes into account a characteristic of the given converter stage and characteristic(s) of one or more earlier converter stages. - View Dependent Claims (24, 25, 26, 27)
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Specification