Efficient calibration of errors in multi-stage analog-to-digital converter

• US 9,503,116 B2
• Filed: 12/01/2015
• Issued: 11/22/2016
• Est. Priority Date: 12/17/2014
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Otte, Eric, Bray, Jeffrey Paul, Speir, Carroll C.
• Primary Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US14/955,916
• Publication Number:
  US 20160182073A1
• Time in Patent Office: 357 Days
• Field of Search: 341/120, 341/122, 341/118, 341/155, 341/156
• US Class Current: 1/1
• CPC Class Codes: H03M 1/1019 by storing a corrected or correction value in a digital look-up table
• CPC Class Codes: H03M 1/1028 at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/121 Interleaved, i.e. using multiple converters or converter parts for one channel
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H03M 1/128 at random intervals, e.g. digital alias free signal processing [DASP]
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter
• CPC Class Codes: H03M 1/462 Details of the control circuitry, e.g. of the successive approximation register
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array
• CPC Class Codes: H03M 3/382 at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
• CPC Class Codes: H03M 3/498 Variable sample rate

Abstract

Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Claims

1. A multi-stage analog-to-digital converter with digitally assisted calibration, the multi-stage analog-to-digital converter comprising:

analog-to-digital converter stages in cascade, each analog-to-digital converter stage for generating a respective output code and a respective amplified output residue signal;

wherein for each analog-to-digital converter stage, the multi-stage analog-to-digital converter further comprises;

a dedicated memory element for storing correction terms;

a multiplexer selecting one of the correction terms in the dedicated memory element based on the respective output code; and

circuitry for correcting an error of the multi-stage analog-to-digital converter based on the selected correction term; and

digital circuitry for computing the correction terms in the dedicated memory elements, wherein computing correction terms used for a given analog-to-digital converter stage takes into account an error term from one or more earlier analog-to-digital converter stages.

2. The multi-stage analog-to-digital converter of claim 1, wherein the circuitry for correcting the error comprises an adder to add the correction term to a sum of the respective output code multiplied by a predetermined weight and the respective amplified output residue signal.

3. The multi-stage analog-to-digital converter of claim 1, wherein the digital circuitry is a microprocessor on-chip with the analog-to-digital converter stages configured to execute instructions to compute the correction terms.

4. The multi-stage analog-to-digital converter of claim 1, wherein computing correction terms used for the given analog-to-digital converter further takes into account an interleaving error term of the multi-stage analog-to-digital converter.

5. The multi-stage analog-to-digital converter of claim 1, wherein:

the analog-to-digital converter stages comprises a first stage and a second stage following the first stage; and

computing correction terms for the second stage comprises computing a first cumulative gain term which includes an interstage gain error of the first stage and an interstage gain error of the second stage.

6. The multi-stage analog-to-digital converter of claim 1, wherein computing correction terms comprises:

determining a gain correction term for the given analog-to-digital converter stage;

determining a capacitor error term per output code of the given analog-to-digital converter stage; and

adding each capacitor error term by the gain correction term multiplied by an output code to which the capacitor error term corresponds to obtain the correction terms selectable by the output codes.

7. The multi-stage analog-to-digital converter of claim 1, wherein computing correction terms comprises:

determining a gain correction term for the given analog-to-digital converter stage;

determining a linearity error term per output code of the given analog-to-digital converter stage; and

adding each linearity error term by the gain correction term multiplied by an output code to which the linearity error term corresponds to obtain the correction terms selectable by the output codes.

8. The multi-stage analog-to-digital converter of claim 1, wherein for each analog-to-digital converter stage, the multi-stage analog-to-digital converter further comprises:

a further dedicated memory element for storing further correction terms; and

a further multiplexer selecting one of the further correction terms in the further dedicated memory element based on a delayed version of the respective output code;

wherein correcting an error of the multi-stage analog-to-digital converter based on the selected correction term by the adder is further based on the selected further correction term.

9. The multi-stage analog-to-digital converter of claim 1, wherein:

the analog-to-digital converter stages comprises a first stage and a second stage following the first stage; and

computing correction terms for the second stage comprises computing a first cumulative linear filter which includes a linear filter corresponding to the first stage and a linear filter corresponding to the second stage.

10. The multi-stage analog-to-digital converter of claim 9, wherein:

computing the first cumulative linear filter comprises computing a convolution of taps of the linear filter corresponding to the first stage and taps of the linear filter corresponding to the second stage.

11. A digitally assisted method for calibrating an analog-to-digital converter having multiple stages of analog-to-digital conversion, the method comprising:

measuring, by dedicated circuitry, one or more characteristics associated with the analog-to-digital converter, wherein the multiple stages generate respective output codes and respective residue signals;

computing, by digital circuitry on-chip with the analog-to-digital converter, correction terms to be used for correcting residue signals of the multiple stages based on the measured errors, wherein computing correction terms used for a given stage takes into account a characteristic(s) measured for one or more earlier stages; and

writing, by the digital circuitry, the correction terms to separate look up tables provided for each residue signal to be corrected, wherein each look up table is indexed by output codes of a respective stage.

12. The digitally assisted method of claim 11, wherein:

the one or more characteristics measured by the dedicated circuitry comprises interstage gain errors of the respective stages.

13. The digitally assisted method of claim 12, wherein measuring the interstage gain errors comprises:

injecting a random signal to a particular stage; and

removing the random signal based on a previously determined gain of the particular stage to measure an interstage gain error of the particular stage.

14. The digitally assisted method of claim 13, wherein the random signal is a two-level pseudo-random signal.

15. The digitally assisted method of claim 14, further comprising:

correlating, by the dedicated circuitry comprising correlator circuitry, the random signal with an error signal left behind after the random signal is removed.

16. The digitally assisted method of claim 15, further comprising:

reading, by the digital circuitry, correlation measurements made by the dedicated circuitry; and

updating the interstage gain error of the particular stage based on the correlation measurements and a predetermined coefficient controlling how quickly the interstage gain error is to be updated.

17. The digitally assisted method of claim 11, wherein computing correction terms used for the given stage comprises multiplying an interstage gain error term for the given stage and one or more interstage gain error terms from the one or more earlier stages.

18. The digitally assisted method of claim 11, wherein computing correction terms used for the given stage comprises combining linear filter for the given stage and linear filter(s) of the one or more earlier stages.

19. The digitally assisted method of claim 11, wherein computing correction terms comprises:

determining a gain correction term for the given stage;

determining a capacitor error term per output code of the given stage; and

adding each capacitor error term by the gain correction term multiplied by an output code to which the capacitor error term corresponds to obtain the correction terms selectable by the output codes.

20. An apparatus comprising:

cascaded means having stages for generating respective output codes and respective residue signals;

storage means for storing correction terms selectable by a respective output code;

means for correcting respective residue signals based on selected correction terms; and

means on-chip with the cascaded means for updating correction terms in the storage means based on measured characteristics, wherein updating the correction terms used for a given stage of the cascaded means takes into account the measured characteristics for the given stage of the cascaded means and one or more earlier stage(s) of the cascaded means.

21. The apparatus of claim 20, further comprising:

calibration means for measuring characteristics of the cascaded means.

22. The apparatus of claim 20, wherein the storage means comprises a plurality of parts, each part dedicated to a corresponding stage of the cascaded means.

23. A multi-stage converter with digitally assisted calibration, the multi-stage converter comprising:

converter stages in cascade;

one or more memory elements for storing correction terms;

circuitry for adjusting a particular converter stage based on a selected correction term; and

digital circuitry for computing the correction terms in the one or more memory elements, wherein computing correction terms used for a given converter stage takes into account a characteristic of the given converter stage and characteristic(s) of one or more earlier converter stages.

24. The multi-stage converter of claim 23, wherein the converter stages generate a respective output code and a respective amplified output residue signal.

25. The multi-stage converter of claim 24, wherein the circuitry for adjusting the particular converter stage comprises an adder to add the selected correction term to a sum of the respective output code multiplied by a predetermined weight and the respective amplified output residue signal.

26. The multi-stage converter of claim 23, wherein the selected correction term is selected based on an output code generated by the particular converter stage.

27. The multi-stage converter of claim 23, wherein the one or more memory elements comprises one or more lookup tables.