SMS4 acceleration hardware

• US 9,503,256 B2
• Filed: 12/24/2014
• Issued: 11/22/2016
• Est. Priority Date: 12/24/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Yap, Kirk, Wolrich, Gilbert, Satpathy, Sudhir, Gulley, Sean, Gopal, Vinodh, Mathew, Sanu, Feghali, Wajdi
• Primary Examiner(s): Chai, Longbit
• Application Number:
  US14/582,707
• Publication Number:
  US 20160191238A1
• Time in Patent Office: 699 Days
• Field of Search: 380/44
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 2209/122 Hardware reduction or efficient architectures
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/0822 using key encryption key

Abstract

Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.

Claims

1. An apparatus comprising:

SMS4 acceleration hardware to execute a round of encryption and a round of key expansion; and

key transformation hardware to transform an encryption round key into a different decryption round key to provide for the SMS4 acceleration hardware to execute a round of decryption according to a SMS4 cryptographic algorithm.

2. The apparatus of claim 1, including a first datapath for the round of encryption and a second datapath for the round of key expansion.

3. The apparatus of claim 2, wherein the round of encryption and the round of key expansion are executed concurrently.

4. The apparatus of claim 3, wherein the round of encryption uses a round key generated during a previous round of key expansion.

5. The apparatus of claim 1, including a shared datapath for the round of encryption and the round of key expansion.

6. The apparatus of claim 5, wherein the round of encryption and the round of key expansion are executed in alternate clock cycles.

7. The apparatus of claim 6, wherein the round of encryption uses a round key generated during a previous round of key expansion.

8. The apparatus of claim 1, including a multiplexer to select a first decryption round key from a first input and a second through a thirty-second decryption round key from a second input.

9. The apparatus of claim 8, wherein the multiplexer is also to select a first through a thirty-second encryption round key from the second input.

10. The apparatus of claim 1, including a shared datapath for a first through a thirty-second decryption round keys and a first through a thirty-second encryption round key.

11. The apparatus of claim 1, wherein the key transformation hardware is to endian reverse a twenty-ninth through a thirty-second encryption round key to generate an intermediate result.

12. The apparatus of claim 11, wherein the key transformation hardware is also to perform an XOR operation on the intermediate result and a system parameter.

13. The apparatus of claim 1, wherein the key transformation hardware is to endian reverse a thirty-third through a thirty-sixth encryption round key to generate an intermediate result.

14. The apparatus of claim 13, wherein the key transformation hardware is also to perform an XOR operation on the intermediate result and a system parameter.

15. A method comprising:

executing a round of SMS4 encryption using SMS4 acceleration hardware;

executing a round of key expansion using the SMS4 acceleration hardware;

transforming an encryption round key to a different decryption round key to provide for executing a round of SMS4 decryption using the SMS4 acceleration hardware according to a SMS4 cryptographic algorithm.

16. The apparatus of claim 15, wherein the round of SMS4 encryption and the round of key expansion are executed concurrently.

17. The method of claim 15, wherein the round of encryption and the round of key expansion are executed in alternate clock cycles.

18. The method of claim 15, wherein transforming the encryption round key include endian reversing four encryption round keys to generate an intermediate result.

19. The method of claim 18, wherein transforming the encryption round key also includes performing an XOR operation on the intermediate result and a system parameter.

20. A processor device comprising:

instruction hardware to receive an SMS4 instruction; and

execution hardware to execute the SMS4 instruction, the execution hardware including;

SMS4 acceleration hardware to execute a round of encryption and a round of key expansion, and key transformation hardware to transform an encryption round key to generate a different decryption round key to provide for the SMS4 acceleration hardware to execute a round of decryption according to a SMS4 cryptographic algorithm.