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Pattern suppression in logic for wafer inspection

  • US 9,506,873 B2
  • Filed: 04/09/2015
  • Issued: 11/29/2016
  • Est. Priority Date: 04/15/2014
  • Status: Active Grant
First Claim
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1. A system configured to detect defects on a wafer, comprising:

  • an illumination subsystem configured to direct light to at least one spot on a wafer, wherein the illumination subsystem comprises at least one light source;

    a scanning subsystem configured to cause the at least one spot to be scanned over the wafer;

    one or more detection channels, wherein at least one of the one or more detection channels comprises;

    a detector configured to detect light scattered from the at least one spot on the wafer and to generate output responsive to the detected scattered light; and

    at least one element configured to block one or more first portions of the light scattered from the at least one spot from reaching the detector while allowing one or more second portions of the light scattered from the at least one spot to be detected by the detector, wherein the one or more first portions of the light are scattered from one or more patterned features formed in a logic region on the wafer, wherein the one or more second portions of the light are not scattered from the one or more patterned features, and wherein the one or more detection channels do not comprise any imaging detectors; and

    a computer subsystem configured to detect defects on the wafer based on the output.

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