Pattern suppression in logic for wafer inspection

• US 9,506,873 B2
• Filed: 04/09/2015
• Issued: 11/29/2016
• Est. Priority Date: 04/15/2014
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation (KLA Corporation)
• Original Assignee: KLA-Tencor Corporation (KLA Corporation)
• Inventors: Gaind, Vaibhav, Amthul, Nisha
• Primary Examiner(s): Punnoose, Roy M
• Application Number:
  US14/682,822
• Publication Number:
  US 20150293035A1
• Time in Patent Office: 600 Days
• Field of Search: 356/237.5
• US Class Current: 1/1
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 2201/10 Scanning

Abstract

Methods and systems for detecting defects on a wafer are provided. One system includes an illumination subsystem configured to direct light to at least one spot on a wafer. The system also includes at least one element configured to block first portion(s) of light scattered from the at least one spot from reaching a detector while allowing second portion(s) of the light scattered from the at least one spot to be detected by the detector. The first portion(s) of the light are scattered from one or more patterned features in a logic region on the wafer. The second portion(s) of the light are not scattered from the one or more patterned features. The detector is not an imaging detector. The system further includes a computer subsystem configured to detect defects on the wafer based on output of the detector.

Claims

1. A system configured to detect defects on a wafer, comprising:

an illumination subsystem configured to direct light to at least one spot on a wafer, wherein the illumination subsystem comprises at least one light source;

a scanning subsystem configured to cause the at least one spot to be scanned over the wafer;

one or more detection channels, wherein at least one of the one or more detection channels comprises;

a detector configured to detect light scattered from the at least one spot on the wafer and to generate output responsive to the detected scattered light; and

at least one element configured to block one or more first portions of the light scattered from the at least one spot from reaching the detector while allowing one or more second portions of the light scattered from the at least one spot to be detected by the detector, wherein the one or more first portions of the light are scattered from one or more patterned features formed in a logic region on the wafer, wherein the one or more second portions of the light are not scattered from the one or more patterned features, and wherein the one or more detection channels do not comprise any imaging detectors; and

a computer subsystem configured to detect defects on the wafer based on the output.

2. The system of claim 1, wherein the one or more patterned features comprise one or more aperiodic patterned features.

3. The system of claim 1, wherein the one or more patterned features comprise one or more non-repeating patterned features.

4. The system of claim 1, wherein the one or more patterned features comprise one or more repeating patterned features.

5. The system of claim 1, wherein the at least one element is not configured for Fourier filtering of the light scattered from the at least one spot due to the one or more patterned features.

6. The system of claim 1, wherein the scanning subsystem is further configured to cause the at least one spot to be scanned over only one or more portions of the logic region formed in one or more dies on the wafer.

7. The system of claim 6, wherein the one or more portions of the logic region correspond to micro care areas on the wafer.

8. The system of claim 6, wherein each of the one or more portions of the logic region is designed to have the same patterned features formed therein.

9. The system of claim 1, wherein the scanning subsystem is further configured to cause the at least one spot to be scanned over only one or more first portions of the logic region formed in one or more dies on the wafer and one or more second portions of the logic region formed in the one or more dies on the wafer, wherein the one or more patterned features formed in the one or more first portions of the logic region have one or more characteristics that are different than one or more characteristics of the one or more patterned features formed in the one or more second portions of the logic region, and wherein the system is further configured to alter the at least one element depending on whether the one or more first portions of the logic region or the one or more second portions of the logic region are being scanned.

10. The system of claim 9, wherein the one or more first portions of the logic region are scanned in the same pass as the one or more second portions of the logic region.

11. The system of claim 9, wherein the one or more first portions of the logic region are scanned in one pass and the one or more second portions of the logic region are scanned in another pass.

12. The system of claim 1, wherein the system is further configured to alter one or more characteristics of the at least one element based on one or more characteristics of the one or more patterned features.

13. The system of claim 1, wherein one or more characteristics of the at least one element are determined based on one or more characteristics of the one or more patterned features.

14. The system of claim 1, wherein the at least one of the one or more detection channels further comprises a collector configured to collect the light scattered from the at least one spot on the wafer, and wherein the collector is not an imaging collector.

15. The system of claim 1, wherein blocking of the scattered light from the one or more patterned features does not alter a resolution of the system.

16. The system of claim 1, wherein the computer subsystem is further configured to create at least one image of the logic region based on the output of the detector and to detect the defects on the wafer based on the at least one image, and wherein the one or more patterned features cannot be resolved in the at least one image due to blocking of the one or more first portions of the light by the at least one element.

17. The system of claim 1, wherein the illumination subsystem is further configured to direct the light to the at least one spot on the wafer at one or more angles of incidence comprising at least an oblique angle of incidence, and wherein the at least one light source comprises at least one laser.

18. The system of claim 1, wherein the at least one light source comprises only one or more narrowband light sources.

19. The system of claim 1, wherein the illumination subsystem is further configured to direct the light to two or more of the at least one spot on the wafer simultaneously.

20. A method for detecting defects on a wafer, comprising:

directing light to at least one spot on a wafer;

scanning the at least one spot over the wafer;

blocking one or more first portions of light scattered from the at least one spot from reaching a detector while allowing one or more second portions of the light scattered from the at least one spot to be detected by the detector, wherein the one or more first portions of the light are scattered from one or more patterned features formed in a logic region on the wafer, wherein the one or more second portions of the light are not scattered from the one or more patterned features, and wherein the detector is not an imaging detector;

detecting light scattered from the at least one spot on the wafer with the detector thereby generating output responsive to the detected scattered light; and

detecting defects on the wafer based on the output.