Single core wakeup multi-core synchronization mechanism

• US 9,507,404 B2
• Filed: 05/19/2014
• Issued: 11/29/2016
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Parks, Terry, Bean, Brent, Gaskins, Stephan
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US14/281,621
• Publication Number:
  US 20150067214A1
• Time in Patent Office: 925 Days
• Field of Search: 713300-340
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

Claims

1. A microprocessor, comprising:

a plurality of cores;

a cache memory shared by the cores; and

a control unit, configured to individually put each of the cores to sleep by stopping a clock signal to the core;

wherein each of the cores is configured to execute a sleep instruction and in response to make a respective request of the control unit to put the core to sleep;

wherein the control unit is configured to;

put each of the cores to sleep in response to the respective request; and

detect when all of the cores have made the respective request to be put to sleep and in response to wakeup only a last of the cores to make the respective request;

wherein the last of the cores is configured to;

write back and invalidate the shared cache memory and indicate that the shared cache memory has been invalidated; and

make a request to the control unit to put the last core back to sleep;

wherein the control unit is configured to;

put the last core back to sleep and continuously keep the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory has been invalidated, and is put back to sleep.

2. The microprocessor of claim 1, wherein the control unit is further configured to:

detect when all of the cores have made the respective request to be put to sleep and in response to automatically block interrupt requests to all but the last core.

3. The microprocessor of claim 1,

wherein the respective request of the control unit to put the core to sleep further includes a request of the control unit to remove power from the core;

wherein to put each of the cores to sleep in response to the respective request to remove power from the core, the control unit is configured to cause power to be removed from the core.

4. The microprocessor of claim 1, wherein each of the cores comprises microcode that makes the respective request to the control unit to the core to sleep, writes back and invalidates the shared cache memory and indicates that the shared cache memory has been invalidated, and makes the request to the control unit to put the core to sleep.

5. The microprocessor of claim 2, wherein the control unit continues to block the interrupt requests to all but the last core until the last core requests the control unit to unblock the interrupt requests to the other cores.

6. The microprocessor of claim 2,

wherein the control unit is further configured to detect an interrupt request directed to a different one of the cores than the last core and in response to wake up the last core and continue to keep the other cores asleep until the last core requests to unblock the interrupt requests and makes a request to the control unit to put the last core back to sleep;

and

wherein the different one of the cores is configured to service the directed interrupt request and make a request to the control unit to put the different one of the cores back to sleep, in response to which the control unit is configured to automatically block interrupt requests to all the cores but the different one of the cores.

7. The microprocessor of claim 5,

wherein the control unit is further configured to detect a non-directed interrupt request and in response to wake up the last core and continue to keep the other cores asleep while the last core services the non-directed interrupt request and makes a request to the control unit to put the last core back to sleep.

8. The microprocessor of claim 6,

wherein the control unit is further configured to keep all but the different one of the cores asleep until it detects an interrupt request directed to a second different one of the cores than the first different one of the cores and the first different one of the cores requests the control unit to unblock interrupt requests.

9. The microprocessor of claim 7,

wherein the control unit is further configured to keep the other cores asleep until the control unit detects an interrupt request directed to one of the other cores and the last core requests the control unit to unblock interrupt requests to the other cores.

10. A method for saving power with a microprocessor having a plurality of cores, a cache memory shared by the cores, and a control unit, configured to individually put each of the cores to sleep by stopping a clock signal to the core, the method comprising:

by each of the cores, executing a sleep instruction and in response making a respective request of the control unit to put the core to sleep;

by the control unit;

putting each of the cores to sleep in response to the respective request; and

detecting when all of the cores have made the respective request to be put to sleep and in response waking up only a last of the cores to make the respective request;

by the last of the cores;

writing back and invalidating the shared cache memory and indicating that the shared cache memory has been invalidated; and

making a request to the control unit to put the last core back to sleep;

by the control unit;

putting the last core back to sleep and continuously keeping the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory has been invalidated, and is put back to sleep.

11. The method of claim 10, further comprising:

by the control unit, detecting when all of the cores have made the respective request to be put to sleep and in response automatically blocking interrupt requests to all but the last core.

12. The method of claim 10,

wherein the respective request of the control unit to put the core to sleep further includes a request of the control unit to remove power from the core;

wherein said putting each of the cores to sleep in response to the respective request to remove power from the core comprises causing power to be removed from the core.

13. The method of claim 10, wherein each of the cores comprises microcode that performs said making the respective request to the control unit to the core to sleep, said writing back and invalidating the shared cache memory and indicating that the shared cache memory has been invalidated, and making the request to the control unit to put the core to sleep.

14. The method of claim 11, further comprising:

by the control unit, continuing to block the interrupt requests to all but the last core until the last core requests the control unit to unblock the interrupt requests to the other cores.

15. The method of claim 11, further comprising:

by the control unit, detecting an interrupt request directed to a different one of the cores than the last core and in response waking up the last core and continuing to keep the other cores asleep until the last core requests to unblock the interrupt requests and makes a request to the control unit to put the last core back to sleep;

by the different one of the cores, servicing the directed interrupt request and making a request to the control unit to put the different one of the cores back to sleep; and

by the control unit, automatically blocking interrupt requests to all the cores but the different one of the cores in response to the request to put the different one of the cores back to sleep.

16. The method of claim 14, further comprising:

by the control unit, detecting a non-directed interrupt request and in response waking up the last core and continuing to keep the other cores asleep while the last core services the non-directed interrupt request and makes a request to the control unit to put the last core back to sleep.

17. The method of claim 15, further comprising:

by the control unit, keeping all but the different one of the cores asleep until it detects an interrupt request directed to a second different one of the cores than the first different one of the cores and the first different one of the cores requests the control unit to unblock interrupt requests.

18. The method of claim 16, further comprising:

by the control unit, keeping the other cores asleep until the control unit detects an interrupt request directed to one of the other cores and the last core requests the control unit to unblock interrupt requests to the other cores.