Method and system of compiling program code into predicated instructions for execution on a processor without a program counter
First Claim
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1. A computer-implemented method of compiling a program code into predicated instructions, comprising:
- extracting, from control flow of the program code, constraints between instructions of the program code;
solving constraint problem between the instructions by determining and assigning a value to a predicate vector that satisfies the constraints to each of the instructions; and
generating a predicate guard and a predicate update for each of the instructions based on the predicate vector to control sequencing of instruction execution of each of the instructions to turn the instructions into the predicated instructions that can be executed on a processor that does not include any program counter which controls sequencing of instruction execution, wherein the predicate guard and predicate update of an instruction provide sequencing information of the corresponding instruction when the corresponding instruction is executed on the processor that does not include any program counter that controls sequencing of instruction execution, wherein the predicate guard of an instruction controls whether the corresponding instruction should be executed and the predicate update of an instruction updates a predicate register bit of the processor which controls when the corresponding instruction is executed.
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Abstract
A predicated instruction compilation system includes a control flow graph generation module to generate a control flow graph of a program code to be compiled into the predicated instructions to be executed on a processor that does not include any program counter. Each of the instructions includes a predicate guard and a predicate update. The compilation system also includes a control flow transformation module to automatically generate the predicate guard and an update to the predicate state on the processor. A computer-implemented method of compiling a program code into predicated instructions is also described.
23 Citations
25 Claims
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1. A computer-implemented method of compiling a program code into predicated instructions, comprising:
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extracting, from control flow of the program code, constraints between instructions of the program code; solving constraint problem between the instructions by determining and assigning a value to a predicate vector that satisfies the constraints to each of the instructions; and generating a predicate guard and a predicate update for each of the instructions based on the predicate vector to control sequencing of instruction execution of each of the instructions to turn the instructions into the predicated instructions that can be executed on a processor that does not include any program counter which controls sequencing of instruction execution, wherein the predicate guard and predicate update of an instruction provide sequencing information of the corresponding instruction when the corresponding instruction is executed on the processor that does not include any program counter that controls sequencing of instruction execution, wherein the predicate guard of an instruction controls whether the corresponding instruction should be executed and the predicate update of an instruction updates a predicate register bit of the processor which controls when the corresponding instruction is executed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A non-transitory computer-readable medium having sequences of instructions, the sequences of instructions including instructions which, when executed, cause a processor to perform program code compilation of a program code into predicated instructions, comprising:
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extracting, from control flow of the program code, constraints between instructions of the program code; solving constraint problem between the instructions of the program code by determining and assigning a value to a predicate vector that satisfies the constraints to each of the instructions of the program code; and generating a predicate guard and a predicate update for each of the instructions of the program code based on the predicate vector to control sequencing of instruction execution of each of the instructions of the program code to turn the instructions of the program code into the predicated instructions that can be executed on a processor that does not include any program counter which controls sequencing of instruction execution, wherein the predicate guard and predicate update of an instruction of the program code provide sequencing information of the corresponding instruction when the corresponding instruction is executed on the processor that does not include any program counter that controls sequencing of instruction execution, wherein the predicate guard of an instruction of the program code controls whether the corresponding instruction should be executed and the predicate update of an instruction updates a predicate register bit of the processor which controls when the corresponding instruction is executed. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A predicated instruction compilation system, comprising:
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a processor; a memory coupled to the processor; a software compiler stored on the memory and executed by the processor to compile instructions of a program code into predicated instructions, further comprising a control flow graph generation module to generate a control flow graph of the program code to be compiled into the predicated instructions for execution on an external processor that does not include any program counter which controls sequencing of instruction execution; and a control flow transformation module to automatically generate a predicate guard and a predicate update for each of the instruction from the control flow graph such that the predicated instructions can be executed on a processor that does not include any program counter which controls sequencing of instruction execution, wherein the predicate guard and predicate update of an instruction provide sequencing information of the corresponding instruction when the corresponding instruction is executed on the processor that does not include any program counter that controls sequencing of instruction execution, wherein the predicate guard of an instruction controls whether the corresponding instruction should be executed and the predicate update of an instruction updates a predicate register bit of the processor which controls when the corresponding instruction is executed. - View Dependent Claims (17, 18, 19, 20)
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21. An apparatus for compiling program code into predicated instructions, comprising:
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means for generating, from control flow of the program code, constraints between instructions of the program code; means for solving constraint problem by determining and assigning a value to a predicate vector that satisfies the constraints to each of the instructions; and means for generating a predicate guard and a predicate update for each of the instructions based on the predicate vector to control sequencing of instruction execution of each of the instructions, wherein the predicated instructions can be executed on a processor that does not include any program counter which controls sequencing of instruction execution, wherein the predicate guard and predicate update of an instruction provide sequencing information of the corresponding instruction when the corresponding instruction is executed on the processor that does not include any program counter that controls sequencing of instruction execution, wherein the predicate guard of an instruction controls whether the corresponding instruction should be executed and the predicate update of an instruction updates a predicate register bit of the processor which controls when the corresponding instruction is executed. - View Dependent Claims (22, 23, 24, 25)
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Specification