Store forwarding for data caches

• US 9,507,725 B2
• Filed: 12/28/2012
• Issued: 11/29/2016
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kosinski, Steffen, Latorre, Fernando, Cooray, Niranjan, Shwartsman, Stanislav, Kalifon, Ethan, Mohandru, Varun, Lopez, Pedro, Aviram-Rosenfeld, Tom, Topp, Jaroslav, Zei, Li-Gao
• Primary Examiner(s): Rojas, Midys
• Assistant Examiner(s): Matin, Tasnima
• Application Number:
  US13/729,945
• Publication Number:
  US 20140189250A1
• Time in Patent Office: 1,432 Days
• Field of Search: 711/113, 711118-146
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array

Abstract

A bit or other vector may be used to identify whether an address range entered into an intermediate buffer corresponds to most recently updated data associated with the address range. A bit or other vector may also be used to identify whether an address range entered into an intermediate buffer overlaps with an address range of data that is to be loaded. A processing device may then determine whether to obtain data that is to be loaded entirely from a cache, entirely from an intermediate buffer which temporarily buffers data destined for a cache until the cache is ready to accept the data, or from both the cache and the intermediate buffer depending on the particular vector settings. Systems, devices, methods, and computer readable media are provided.

Claims

1. A memory device comprising:

a data buffer storing data destined for a cache until the cache is ready to accept the data;

a store address buffer storing addresses of data stored in the data buffer, wherein the addresses are stored as address entries in the store address buffer, and wherein each address entry includes an address range;

a demarcator to identify (i) those address entries in the store address buffer that include an address range at least partially overlapping with an address of data to be loaded and (ii) whether or not the address range of each respective address entry in the store address buffer has been overwritten by an address range of a later added address entry; and

a processing device to load at least a subset of data from the data buffer instead of the cache if only one address entry in the store address buffer is identified as both having an overlapping address range and as not having its address range been overwritten.

2. The memory device of claim 1, wherein the demarcator identifies a respective address range as not overwritten if the respective address range is only partially overwritten by an address range of a later added address entry.

3. The memory device of claim 1, wherein the address range of at least one of the address entries is a single address.

4. The memory device of claim 1, wherein the address range of at least one of the address entries includes a plurality of addresses.

5. The memory device of claim 1, wherein the processing device (i) executes a secondary conflict resolution procedure to identify data to be loaded if at least two address entries in the store address buffer are each identified as both having an overlapping address range and as not having its address range been overwritten by an address range of a later added address entry, and (ii) stalls other operations until the secondary conflict resolution procedure is complete.

6. A method comprising:

comparing an address range of data to be loaded to address ranges of a plurality of address entries, wherein the address entries are temporarily stored in an intermediate buffer together with associated data until a cache is ready to accept the associated data;

identifying those address entries, if any, that have an address range at least partially overlapping with the address range of the data to be loaded, using a processing device;

identifying whether each of the address entries includes an address range that has been overwritten by an address range of a later added address entry;

loading the data to be loaded from the cache if no address entries are identified as having an overlapping address range; and

loading at least a subset of the data to be loaded from the intermediate buffer if only one of the address entries is identified as both having an overlapping address range and not having its address range been overwritten.

7. The method of claim 6, further comprising, loading the data to be loaded entirely from the intermediate buffer if the address range of the only one address entry identified as both having an overlapping address range and not having its address range been overwritten completely overlaps the address range of the data to be loaded.

8. The method of claim 6, further comprising, loading the data to be loaded partially from the intermediate buffer and partially from the cache if the address range of the only one address entry identified as both having an overlapping address range and not having its address range been overwritten only partially overlaps the address range of the data to be loaded.

9. The method of claim 8, further comprising, loading data corresponding to the partially overlapping address range from the intermediate buffer and loading any remaining portions of the data to be loaded from the cache.

10. The method of claim 6, further comprising:

stalling the loading of the data to be loaded if more than one of the address entries is identified as both having an overlapping address range and not having its address range been overwritten;

retrieving a sequence in which address entries are buffered;

identifying from the sequence an order in which the data to be loaded is stored in the intermediate buffer; and

loading most recently updated data from the intermediate buffer based on the identified order.

11. The method of claim 6, further comprising, repeating the method if no address entries are identified as having an overlapping address range, before loading the data to be loaded from the cache.

12. The method of claim 6, further comprising:

adding a first bit vector and a second bit vector to each address entry stored in the intermediate buffer;

setting the first bit vector to a first value to indicate that a respective address range has not been overwritten by an address range of a later added address entry; and

setting the second bit vector to a second value to indicate that the respective address range at least partially overlaps with the address range of the data to be loaded.

13. The method of claim 12, further comprising, only loading data from the intermediate buffer if at least one address entry has the first vector set to the first value and the second vector set to the second value.

14. The method of claim 12, wherein the first value and the second value are a same value.

15. A non-transitory computer readable medium storing instructions that, when executed by a processing device, cause the processing device to:

compare an address range of data to be loaded to a plurality of address ranges of address entries, wherein the address entries are temporarily stored in an intermediate buffer together with associated data until a cache is ready to accept the associated data;

identify those address entries, if any, that have an address range at least partially overlapping with the address range of the data to be loaded;

identify whether the address range of each of the address entries has been overwritten by an address range of a later added address entry;

load the data to be loaded from the cache if no address entries are identified as having an overlapping address range; and

load at least a subset of the data to be loaded from the intermediate buffer if only one of the address entries is identified as both having an overlapping address range and not having its address range been overwritten.

16. The non-transitory computer readable medium of claim 15, further comprising additional instructions that, when executed by the processing device, cause the processing device to:

set a first bit vector added to each address entry in the intermediate buffer to a first value to indicate that a respective address range has not been overwritten by an address range of a later added address entry;

set a second bit vector added to each address entry in the intermediate buffer to a second value to indicate that the respective address range at least partially overlaps with the address range of the data to be loaded; and

load data from the intermediate buffer if at least one address entry has the first vector set to the first value and the second vector set to the second value.

17. The non-transitory computer readable medium of claim 15, wherein the intermediate buffer includes a data buffer storing the data associated with the address entries and a store address buffer storing the address entries.

18. A system comprising:

a cache;

a data buffer storing data destined for a cache until the cache is ready to accept the data;

a store address buffer storing, for each data entry stored in the data buffer, an associated address entry, a first vector, and a second vector, wherein the first vector is set to a first value if an address range of a respective address entry has not been overwritten by an address range of a later added address entry, and wherein the second vector is set to a second value if the address range of the respective address entry at least partially overlaps with an address range of data to be loaded; and

a processing device configured to load the data to be loaded;

(i) from the cache if the first and the second vectors are not set to the respective first and second values for any of the address entries in the store address buffer and (ii) at least in part from the data buffer if the first and the second vectors are set to the respective first and second values for only one of the address entries in the store address buffer.

19. The system of claim 18, wherein the first and second vectors are bit vectors.

20. The system of claim 18, wherein the processing device is further configured to execute a secondary conflict resolution procedure to identify the data to be loaded if the first and the second vectors are set to the respective first and second values for at least two of the address entries in the store address buffer.