Configurable memory circuit system and method

• US 9,507,739 B2
• Filed: 10/26/2015
• Issued: 11/29/2016
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Schakel, Keith R., Smith, Michael John Sebastian, Wang, David T., Weber, Frederick Daniel
• Primary Examiner(s): Rigol, Yaima
• Application Number:
  US14/922,388
• Publication Number:
  US 20160048466A1
• Time in Patent Office: 400 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/4063 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Claims

1. A sub-system, comprising:

an interface circuit adapted for coupling with a plurality of physical memory circuits and a system, the interface circuit configured to;

interface the plurality of physical memory circuits and the system for emulating a virtual memory circuit having a refresh cycle time constraint that is different from a refresh cycle time constraint of the plurality of physical memory circuits;

receive a refresh command from the system directed to the virtual memory circuit;

in response to receiving the refresh command from the system directed to the virtual memory circuit, determine a staggered sequence of timings for issuing refresh commands to the plurality of physical memory circuits, wherein the staggered sequence of timings satisfy the refresh cycle time constraint of the virtual memory circuit and the refresh cycle time constraint of the plurality of physical memory circuits; and

based on the staggered sequence of timings, issue refresh commands to respective physical memory circuits,

wherein the refresh cycle time constraint of the virtual memory circuit specifies a minimum refresh cycle time (tRFC) associated with the virtual memory circuit, and

wherein the first refresh command and the second refresh command are issued within a span of time specified by the tRFC associated with the virtual memory circuit.

2. The sub-system of claim 1, wherein interfacing the plurality of physical memory circuits and the system for emulating the virtual memory circuit comprises:

using the plurality of physical memory circuits to emulate the virtual memory circuit; and

presenting the virtual memory circuit to the system, wherein the virtual memory circuit appears to the system as having the refresh cycle time constraint of the virtual memory circuit.

3. The sub-system of claim 1, wherein issuing refresh commands to respective physical memory circuits comprises:

based on the staggered sequence of timings, issuing a first refresh command to a first physical memory circuit of the plurality of physical memory circuits; and

based on the staggered sequence of timings, issuing a second refresh command to a second physical memory circuit of the plurality of physical memory circuits, wherein the first refresh command and the second refresh command are issued at different times.

4. The sub-system of claim 3, wherein issuing the first refresh command to the first physical memory circuit of the plurality of physical memory circuits comprises issuing the first refresh command to a group of physical memory circuits that include the first physical memory circuit.

5. The sub-system of claim 3, wherein issuing the first refresh command to the first physical memory circuit of the plurality of physical memory circuits comprises issuing a command to the second physical memory circuit to bring the second physical memory circuit into a power down mode.

6. The sub-system of claim 3, wherein the interface circuit is configured to:

after issuing the first refresh command and the second refresh command, issuing commands to the first physical memory circuit and the second physical memory circuit to bring the first physical memory circuit and the second physical memory circuit into a precharge power down mode.

7. The sub-system of claim 1,

wherein a capacity of the virtual memory circuit is larger than a capacity of each of the plurality of physical memory circuits, and

wherein the refresh cycle time constraint of the virtual memory circuit is larger than the refresh cycle time constraint of the plurality of physical memory circuits.

8. An apparatus, comprising:

a plurality of physical memory circuits;

an interface circuit electrically coupled to the plurality of physical memory circuits and a system, the interface circuit configured to;

interface the plurality of physical memory circuits and the system for emulating a virtual memory circuit having a refresh cycle time constraint that is different from a refresh cycle time constraint of the plurality of physical memory circuits;

receive a refresh command from the system directed to the virtual memory circuit;

in response to receiving the refresh command from the system directed to the virtual memory circuit, determine a staggered sequence of timings for issuing refresh commands to the plurality of physical memory circuits, wherein the staggered sequence of timings satisfy the refresh cycle time constraint of the virtual memory circuit and the refresh cycle time constraint of the plurality of physical memory circuits; and

based on the staggered sequence of timings, issue refresh commands to respective physical memory circuits,

wherein the refresh cycle time constraint of the virtual memory circuit specifies a minimum refresh cycle time (tRFC) associated with the virtual memory circuit, and

wherein the first refresh command and the second refresh command are issued within a span of time specified by the tRFC associated with the virtual memory circuit.

9. The apparatus of claim 8, wherein interfacing the plurality of physical memory circuits and the system for emulating the virtual memory circuit comprises:

using the plurality of physical memory circuits to emulate the virtual memory circuit; and

presenting the virtual memory circuit to the system, wherein the virtual memory circuit appears to the system as having the refresh cycle time constraint of the virtual memory circuit.

10. The apparatus of claim 8, wherein issuing refresh commands to respective physical memory circuits comprises:

based on the staggered sequence of timings, issuing a first refresh command to a first physical memory circuit of the plurality of physical memory circuits; and

based on the staggered sequence of timings, issuing a second refresh command to a second physical memory circuit of the plurality of physical memory circuits, wherein the first refresh command and the second refresh command are issued at different times.

11. The apparatus of claim 10, wherein issuing the first refresh command to the first physical memory circuit of the plurality of physical memory circuits comprises issuing the first refresh command to a group of physical memory circuits that include the first physical memory circuit.

12. The apparatus of claim 10, wherein issuing the first refresh command to the first physical memory circuit of the plurality of physical memory circuits comprises issuing a command to the second physical memory circuit to bring the second physical memory circuit into a power down mode.

13. The apparatus of claim 10, wherein the interface circuit is configured to:

after issuing the first refresh command and the second refresh command, issuing commands to the first physical memory circuit and the second physical memory circuit to bring the first physical memory circuit and the second physical memory circuit into a precharge power down mode.

14. The apparatus of claim 8,

wherein a capacity of the virtual memory circuit is larger than a capacity of each of the plurality of physical memory circuits, and

wherein the refresh cycle time constraint of the virtual memory circuit is larger than the refresh cycle time constraint of the plurality of physical memory circuits.

15. A method, comprising:

interfacing, by an interface circuit, a plurality of physical memory circuits and a system to emulate a virtual memory circuit having a refresh cycle time constraint that is different from a refresh cycle time constraint of the plurality of physical memory circuits;

receiving a refresh command from the system directed to the virtual memory circuit;

in response to receiving the refresh command from the system directed to the virtual memory circuit, determining a staggered sequence of timings for issuing refresh commands to the plurality of physical memory circuits, wherein the staggered sequence of timings satisfy the refresh cycle time constraint of the virtual memory circuit and the refresh cycle time constraint of the plurality of physical memory circuits; and

based on the staggered sequence of timings, issuing refresh commands to respective physical memory circuits,

wherein the refresh cycle time constraint of the virtual memory circuit specifies a minimum refresh cycle time (tRFC) associated with the virtual memory circuit, and

wherein the first refresh command and the second refresh command are issued within a span of time specified by the tRFC associated with the virtual memory circuit.

16. The method of claim 15, wherein interfacing the plurality of physical memory circuits and the system to emulate the virtual memory circuit comprises:

using the plurality of physical memory circuits to emulate the virtual memory circuit; and

presenting the virtual memory circuit to the system, wherein the virtual memory circuit appears to the system as having the refresh cycle time constraint of the virtual memory circuit.

17. The method of claim 15, wherein issuing refresh commands to respective physical memory circuits comprises:

based on the staggered sequence of timings, issuing a first refresh command to a first physical memory circuit of the plurality of physical memory circuits; and

based on the staggered sequence of timings, issuing a second refresh command to a second physical memory circuit of the plurality of physical memory circuits, wherein the first refresh command and the second refresh command are issued at different times.

18. The method of claim 17, wherein the interface circuit is configured to:

after issuing the first refresh command and the second refresh command, issuing commands to the first physical memory circuit and the second physical memory circuit to bring the first physical memory circuit and the second physical memory circuit into a precharge power down mode.

19. The method of claim 15,

wherein a capacity of the virtual memory circuit is larger than a capacity of each of the plurality of physical memory circuits, and

wherein the refresh cycle time constraint of the virtual memory circuit is larger than the refresh cycle time constraint of the plurality of physical memory circuits.

20. A sub-system, comprising:

an interface circuit adapted for coupling with a plurality of physical memory circuits and a system, the interface circuit configured to;

interface the plurality of physical memory circuits and the system for emulating a virtual memory circuit having a refresh cycle time constraint that is different from a refresh cycle time constraint of the plurality of physical memory circuits;

receive a refresh command from the system directed to the virtual memory circuit;

in response to receiving the refresh command from the system directed to the virtual memory circuit, determine a staggered sequence of timings for issuing refresh commands to the plurality of physical memory circuits, wherein the staggered sequence of timings satisfy the refresh cycle time constraint of the virtual memory circuit and the refresh cycle time constraint of the plurality of physical memory circuits; and

based on the staggered sequence of timings, issue refresh commands to respective physical memory circuits, the issuing comprising;

based on the staggered sequence of timings, issue a first refresh command to a first physical memory circuit of the plurality of physical memory circuits and issue a command to a second physical memory circuit of the plurality of physical memory circuits to bring the second physical memory circuit into a power down mode; and

based on the staggered sequence of timings, issue a second refresh command to the second physical memory circuit, wherein the first refresh command and the second refresh command are issued at different times.