Secure BIOS mechanism in a trusted computing system

• US 9,507,942 B2
• Filed: 11/13/2013
• Issued: 11/29/2016
• Est. Priority Date: 11/13/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn
• Primary Examiner(s): Homayounmehr, Farid
• Assistant Examiner(s): SARKER, SANCHIT K
• Application Number:
  US14/079,087
• Publication Number:
  US 20150134975A1
• Time in Patent Office: 1,112 Days
• Field of Search: 713/194
• US Class Current: 1/1
• CPC Class Codes: G06F 21/572 Secure firmware programming, e.g. of basic input output system [BIOS]
• CPC Class Codes: G06F 2221/2139 Recurrent verification

Abstract

An apparatus including a ROM and a microprocessor. The ROM includes BIOS contents that are stored as plaintext and an encrypted digest. The encrypted digest includes an encrypted version of a first digest corresponding to the BIOS contents. The microprocessor is coupled to the BIOS ROM, and includes a tamper timer and a tamper detector. The tamper timer periodically generates an interrupt at a prescribed interval. The tamper detector accesses the BIOS contents and the encrypted digest upon assertion of the interrupt, and directs the microprocessor to generate a second digest corresponding to the BIOS contents and a decrypted digest corresponding to the encrypted digest using the same algorithms and key that were employed to generate the first digest and the encrypted digest, and compares the second digest with the decrypted digest, and precludes operation of the microprocessor if the second digest and the decrypted digest are not equal.

Claims

1. An apparatus for protecting a basic input/output system (BIOS) in a computing system, the apparatus comprising:

a BIOS read only memory (ROM), comprising;

BIOS contents, wherein said BIOS contents are stored as plaintext; and

an encrypted message digest, wherein said encrypted message digest comprises an encrypted version of a first message digest that corresponds to said BIOS contents;

a tamper detector, operatively coupled to said BIOS ROM, configured to generate a BIOS check interrupt at a combination of prescribed intervals and event occurrences, and configured to access said BIOS contents and said encrypted message digest upon assertion of said BIOS check interrupt, and configured to direct a microprocessor to generate a second message digest corresponding to said BIOS contents and a decrypted message digest corresponding to said encrypted message digest, and configured to compare said second message digest with said decrypted message digest, and configured to preclude said operation of said microprocessor if said second message digest and said decrypted message digest are not equal; and

a random number generator disposed within said microprocessor, wherein said random number generator generates a random number at completion of a current BIOS check, which is employed to set a following prescribed interval, whereby said prescribed intervals are randomly varied.

2. The apparatus as recited in claim 1, wherein said BIOS ROM is disposed separately from said tamper timer and said tamper detector on a system board of the computing system.

3. The apparatus as recited in claim 1, wherein said microprocessor employs the Secure Hash Algorithm to generate said second message digest.

4. The apparatus as recited in claim 1, wherein said microprocessor employs the Advanced Encryption Standard algorithm to generate said decrypted message digest.

5. The apparatus as recited in claim 1, wherein said microprocessor comprises a dedicated crypto/hash unit disposed within execution logic, and wherein said crypto/hash unit generates said second message digest and said decrypted message digest, and wherein said key is exclusively accessed by said crypto/hash unit.

6. The apparatus as recited in claim 1, wherein said random number generator is disposed within execution logic in said microprocessor.

7. The apparatus as recited in claim 5, wherein said key and said tamper timer cannot be accessed by program instructions that are executed by said microprocessor.

8. An apparatus for protecting a basic input/output system (BIOS) in a computing system, the apparatus comprising:

a BIOS read only memory (ROM), comprising;

BIOS contents, wherein said BIOS contents are stored as plaintext; and

an encrypted message digest, wherein said encrypted message digest comprises an encrypted version of a first message digest that corresponds to said BIOS contents; and

a microprocessor, coupled to said BIOS ROM, said microprocessor comprising;

a tamper detector, operatively coupled to said BIOS ROM, configured to generate a BIOS check interrupt at a combination of prescribed intervals and event occurrences, and configured to access said BIOS contents and said encrypted message digest upon assertion of said BIOS check interrupt, and configured to direct said microprocessor to generate a second message digest corresponding to said BIOS contents and a decrypted message digest corresponding to said encrypted message digest, and configured to compare said second message digest with said decrypted message digest, and configured to preclude said operation of said microprocessor if said second message digest and said decrypted message digest are not equal; and

a random number generator disposed within said microprocessor, wherein said random number generator generates a random number at completion of a current BIOS check, which is employed to set a following prescribed interval, whereby said prescribed intervals are randomly varied.

9. The apparatus as recited in claim 8, wherein said BIOS ROM is disposed separately from said tamper timer and said tamper detector on a system board of the computing system.

10. The apparatus as recited in claim 8, wherein said microprocessor employs the Secure Hash Algorithm to generate said second message digest.

11. The apparatus as recited in claim 8, wherein said microprocessor employs the Advanced Encryption Standard algorithm to generate said decrypted message digest.

12. The apparatus as recited in claim 8, said microprocessor further comprising:

a dedicated crypto/hash unit disposed within execution logic, wherein said crypto/hash unit generates said second message digest and said decrypted message digest, and wherein said key is exclusively accessed by said crypto/hash unit.

13. The apparatus as recited in claim 8, wherein said random number generator is disposed within execution logic in said microprocessor.

14. The apparatus as recited in claim 12, wherein said key cannot be accessed by program instructions that are executed by said microprocessor.

15. A method for protecting a basic input/output system (BIOS) in a computing system, the method comprising:

storing BIOS contents as plaintext in a BIOS ROM along with an encrypted message digest that comprises an encrypted version of first message digest that corresponds to the BIOS contents;

generating a BIOS check interrupt that interrupts normal operation of the computing system at a combination of prescribed intervals and event occurrences;

upon assertion of the BIOS check interrupt, accessing the BIOS contents and the encrypted message digest, and generating a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the first encrypted message digest using the same algorithms and key that were employed to generate the first message digest and the encrypted message digest;

comparing the second message digest with the decrypted message digest;

precluding operation of the microprocessor if the second message digest and the decrypted message digest are not equal; and

employing a random number generator within the microprocessor to generate a random number at completion of a current BIOS check, which is employed to set a following prescribed interval, whereby the prescribed intervals are randomly varied.

16. The method as recited in claim 15, further comprising:

separately disposing the BIOS ROM on a system board of the computing system.

17. The method as recited in claim 15, wherein said accessing comprises:

employing the Secure Hash Algorithm to generate the second message digest.

18. The apparatus as recited in claim 15, wherein said accessing further comprises:

employing the Advanced Encryption Standard algorithm to generate the decrypted message digest.

19. The method as recited in claim 15, wherein the microprocessor comprises a dedicated crypto/hash unit disposed within execution logic, and wherein the crypto/hash unit generates the second message digest and the decrypted message digest, and wherein the key is exclusively accessed by the crypto/hash unit.

20. The method as recited in claim 15, wherein the random number generator is disposed within execution logic in the microprocessor.

21. The method as recited in claim 19, wherein the key cannot be accessed by program instructions that are executed by the microprocessor.