Self repair device and method thereof

• US 9,508,456 B1
• Filed: 10/08/2015
• Issued: 11/29/2016
• Est. Priority Date: 06/16/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Shim, Young Bo
• Primary Examiner(s): Le, Toan
• Application Number:
  US14/878,081
• Publication Number:
  US 20160372214A1
• Time in Patent Office: 418 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/78 using programmable devices
• CPC Class Codes: G11C 29/787 using a fuse hierarchy

Abstract

A self repair device may include: an electrical fuse array configured to store bit information of a failed address in a fuse; an electrical fuse controller configured to store a row address or column address corresponding to a failed bit when a failure occurs, generate a repair address by comparing a failed address inputted during a test to the address stored therein, output a rupture enable signal for controlling a rupture operation of the electrical fuse array, and output row fuse set data or column fuse set data in response to the failed address; and a row/column redundancy unit configured to perform a row redundancy or column redundancy operation in response to the row fuse set data or the column fuse set data applied from the electrical fuse array.

Claims

1. A self repair device comprising:

an electrical fuse array configured to store information of a failed address in a fuse;

an electrical fuse controller configured to store a row address or column address corresponding to a failed bit when a failure occurs, generate a repair address by comparing a failed address inputted during a test to the address stored therein, output a rupture enable signal for controlling a rupture operation of the electrical fuse array, and output row fuse set data or column fuse set data in response to the failed address; and

a row/column redundancy unit configured to perform a row redundancy or column redundancy operation in response to the row fuse set data or the column fuse set data applied from the electrical fuse array;

wherein the electrical fuse controller is configured to control the rupture operation when the failed address is a multi-bit address in response to a multi-bit enable signal.

2. The self repair device of claim 1, wherein the electrical fuse controller comprises:

a rupture/boot-up control unit configured to control a rupture and boot-up operation of the electrical fuse array in response to the failed address;

an address selection unit configured to select a row self repair mode or column self repair mode in response to a fuse set select signal;

an address register configured to extract fuse information from the failed address applied from the address selection unit, and store bank information, mat information, and row/column address information on row/column address found to be defective;

a fuse set latch unit configured to store unused fuse set information by searching a fuse region in which the failed address is positioned, during the boot-up operation of the electrical fuse array, and output an unused fuse signal and the rupture enable signal in response to an output of the rupture/boot-up control unit and an output of the address register; and

a data selection unit configured to generate the repair address in response to the unused fuse signal, the output of the rupture/boot-up control unit, and the output of the address register.

3. The self repair device of claim 2, wherein the rupture/boot-up control unit receives a boot-up signal and a rupture signal, outputs a clock signal to the row/column redundancy unit, outputs a row fuse set enable signal and a column fuse set enable signal to the electrical fuse array, and outputs a count signal, a power signal, and a self rupture signal.

4. The self repair device of claim 2, wherein the address selection unit outputs the row address or column address as a select signal in response to a fuse set select signal.

5. The self repair device of claim 2, wherein the address register receives data of a global line, a select signal, an input control signal, and an address select signal, and outputs a bank signal, a mat signal, a select address, and a multi-bit flag signal.

6. The self repair device of claim 5, wherein the global line comprises a global data line, which operates in a specific test mode, is activated to a high level or transitions to a low level when a memory cell of a memory device, which has been accessed during a memory read operation, has passed or failed a test, and transmits, to a data output buffer of the memory device, the information as to whether the memory cell has passed or failed the test.

7. The self repair device of claim 5, wherein the input control signal comprises a pulse signal which controls a pipe register input unit to store the data, which has been loaded in the global line, in a pipe register, while the information as to whether the memory cell has passed or failed the test is transmitted to the data output buffer during the memory read operation.

8. The self repair device of claim 2, wherein the address register comprises:

a plurality of latches configured to store a signal of the global line, a select signal, and an input control signal;

a plurality of address comparators configured to compare outputs of the latches to the signal of the global line and the select signal in response to an address select signal; and

an address combiner configured to combine outputs of the address comparators and output a bank signal, a mat signal, a select address, and a multi-bit flag signal.

9. The self repair device of claim 8, wherein the plurality of address comparators are sequentially selected one by one in response to the address select signal.

10. The self repair device of claim 8, wherein the multi-bit flag signal comprises a signal indicating whether a failed address selected by the address select signal among a plurality of failed addresses stored in the address register is a multi-bit failure.

11. The self repair device of claim 2, wherein the fuse set latch unit receives a fuse set enable signal and a fuse set disable signal which are applied from the electrical fuse array, a count signal applied from the rupture/boot-up control unit, a bank signal, a mat signal, and a multi-bit flag signal which are applied from the address register, and the multi-bit enable signal, and outputs the rupture enable signal and the unused fuse signal.

12. The self repair device of claim 11, wherein the fuse set enable signal comprises a bit signal for enabling a cell array selected by the fuse set select signal among row cell arrays or column cell arrays of the electrical fuse array, and indicates whether the corresponding fuse set is used.

13. The self repair device of claim 11, wherein the fuse set disable signal comprises a bit signal for disabling a cell array selected by the fuse set select signal among row cell arrays or column cell arrays of the electrical fuse array, and indicates whether the corresponding fuse set is a failed fuse set.

14. The self repair device of claim 11, wherein when the multi-bit enable signal has a logic high level, the fuse set latch unit enables the rupture enable signal only in a case where the failed address is a multi-bit address, and

when the multi-bit enable signal has a logic low level, the fuse set latch unit enables the rupture enable signal for all failed addresses, regardless of whether the failed addresses are multi-bit addresses or single-bit addresses.

15. The self repair device of claim 2, wherein the data selection unit selects, according to a self rupture signal, one between memory repair data information and a bank signal, mat signal, or select address information applied from the address register, and outputs the repair address to the electrical fuse array.

16. The self repair device of claim 2, wherein the data selection unit selects an unused fuse set signal inputted from the fuse set latch unit, and outputs an unused fuse set signal found in the failed address region to the electrical fuse array during a boot-up operation.

17. The self repair device of claim 1, wherein the electrical fuse array comprises:

a column cell array configured to be enabled by a column word line, output column fuse set data to the row/column redundancy unit, and output a column fuse set enable signal and a column fuse set disable signal;

a row cell array configured to be enabled by a row word line, output row fuse set data to the row/column redundancy unit, and output a row fuse set enable signal and a row fuse set disable signal;

a first selection unit configured to select one of the row fuse set enable signal and the column fuse set enable signal in response to a fuse set select signal, and output the selected signal as a fuse set enable signal;

a second selection unit configured to select one of the row fuse set disable signal and the column fuse set disable signal in response to the fuse set select signal, and output the selected signal as a fuse set disable signal; and

a cell array control unit configured to generate control signals for controlling the operations of the column cell array and the row cell array.

18. The self repair device of claim 17, wherein the cell array control unit receives a clock, the row fuse set enable signal, the column fuse set enable signal, the rupture enable signal, an unused fuse signal, and the repair address, outputs a signal of the column word line, a column bit line select signal, and a column sense amplifier select signal, and outputs a signal of the row word line, a row bit line select signal, and a row sense amplifier select signal.

19. A self repair method comprising:

selecting a row self repair mode or column self repair mode in response to a fuse set select signal;

storing a row address or column address corresponding to a first failed bit in a latch;

generating a repair address by comparing a failed address, which has been inputted during a test, to the address stored in the latch;

searching unused fuse set information in response to fuse information applied from an electrical fuse array during a boot-up operation;

receiving the repair address, a multi-bit enable signal and the fuse set information, and rupturing the electrical fuse array; and

performing a row redundancy operation or column redundancy operation in response to output data of the electrical fuse array.

20. The self repair method of claim 19, further comprising repeating the above processes on failed bits inputted after the first failed bit.