Method for forming barrier layer for dielectric layers in semiconductor devices

• US 9,508,548 B2
• Filed: 03/31/2014
• Issued: 11/29/2016
• Est. Priority Date: 03/31/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Sheng-Wen, Lin, Yu-Ting, Chang, Che-Hao, You, Wei-Ming, Wang, Ting-Chun
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US14/231,190
• Publication Number:
  US 20150279954A1
• Time in Patent Office: 974 Days
• Field of Search: 438/585, 438/216, 438/591, 438/653, 438/627, 438/643, 438/259, 438/287
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/28026 characterised by the conductor H01L21/28176 takes precedence
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/6659 : with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 : with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming an interfacial layer;

forming a dielectric layer over the interfacial layer;

forming a conductive layer over the dielectric layer;

treating, after the forming the conductive layer, the conductive layer to increase an oxygen-blocking ability of the conductive layer, the treated conductive layer comprising a metal nitride containing a higher nitrogen concentration at a top surface located farthest from the dielectric layer than at a location away from the top surface;

forming a silicon cap over the treated conductive layer;

treating the silicon cap with post-capping anneal (PCA) processes;

forming a gate electrode over the silicon cap; and

forming contacts over the gate electrode.

2. The method of claim 1, wherein the treating is a nitridation process.

3. The method of claim 1, wherein the treating comprises performing a plasma process using a nitrogen-containing process gas.

4. The method of claim 1, wherein the treating comprises increasing a nitrogen concentration of the conductive layer along the top surface.

5. The method of claim 1, wherein the dielectric layer is a high-k dielectric layer.

6. The method of claim 1, wherein the forming the interfacial layer comprises forming an oxide layer using a chemical oxidation process.

7. The method of claim 1, wherein the forming the conductive layer comprises forming a TiN layer.

8. The method of claim 7, wherein the treating comprises forming a TixNy layer along the top surface, a ratio of y:

x being from about 1.0 to about 1.2.

9. A method of forming a semiconductor device, the method comprising:

providing a substrate;

forming a gate dielectric layer over the substrate;

forming a barrier layer over the gate dielectric layer;

increasing a first nitrogen concentration in a top surface of the barrier layer to be greater than a second nitrogen concentration in the barrier layer at a location away from the top surface, the top surface being farthest from the gate dielectric layer;

forming a silicon layer over a surface of the barrier layer;

annealing the silicon layer;

forming a gate electrode over the silicon layer;

forming an inter-layer dielectric over the gate electrode;

patterning the inter-layer dielectric to expose a portion of the gate electrode; and

forming a contact over the gate electrode.

10. The method of claim 9, further comprising forming an interfacial layer prior to forming the gate dielectric layer.

11. The method of claim 10, wherein the forming the interfacial layer comprises forming a chemical oxide layer.

12. The method of claim 9, wherein the increasing is performed at least in part by performing a decoupled plasma nitridation (DPN) process.

13. The method of claim 12, wherein the increasing further comprises annealing after the performing the DPN process.

14. The method of claim 9, wherein the forming the gate electrode comprises forming a metal gate electrode.

15. The method of claim 9, wherein the forming the barrier layer comprises forming a TixNy layer, wherein the first nitrogen concentration is ratio of y:

x after the increasing the first nitrogen concentration is from about 1.0 to about 1.2.

16. The method of claim 9, wherein the forming the gate dielectric layer comprises forming a high-k dielectric layer.

17. The method of claim 9, further comprising, prior to the forming the gate dielectric layer:

forming a dummy gate stack;

forming a dielectric layer, an upper surface of the dielectric layer and an upper surface of the dummy gate stack being coplanar; and

removing the dummy gate stack.

18. A method of forming a semiconductor device, the method comprising:

providing a substrate;

forming a gate dielectric layer over the substrate;

forming a conductive layer over the gate dielectric layer;

performing a nitridation process on the conductive layer, wherein after performing the nitridation process, the conductive layer comprises a first Ti_xN_y layer along a top surface of the conductive layer, a ratio of y;

x being from about 1.0 to about 1.2 at the first Ti_xN_y layer, and the conductive layer comprising a second Ti_xN_y layer at a location away from the top surface of the conductive layer, a ratio of y;

x of about 0.85 to about 0.98 at the second Ti_x N_y layer;

forming a silicon layer over the conductive layer;

treating the silicon layer with post-capping anneal (PCA) processes;

forming a gate electrode over the conductive layer;

forming an inter-layer dielectric over the gate electrode, the inter-layer dielectric having an opening above a portion of the gate electrode; and

forming a contact in the opening above the portion of the gate electrode.

19. The method of claim 18, wherein performing the nitridation process comprises performing a DPN process.

20. The method of claim 18, wherein the forming the gate dielectric layer comprises forming a high-k dielectric layer.