Conductive layer routing

• US 9,508,589 B2
• Filed: 05/20/2014
• Issued: 11/29/2016
• Est. Priority Date: 01/03/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Song, Stanley Seungchul, Rim, Kern, Wang, Zhongze, Xu, Jeffrey Junhao, Chen, Xiangdong, Yeap, Choh Fei
• Primary Examiner(s): SAYADIAN, HRAYR
• Application Number:
  US14/283,162
• Publication Number:
  US 20150194339A1
• Time in Patent Office: 924 Days
• Field of Search: 257/770, 257/741, 257/773, 438/618
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask across active contacts to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts and selectively insulate some of the active contacts. The method also includes depositing a conductive material on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices.

Claims

1. A device including middle-of-line (MOL) layers, the MOL layers comprising:

an isolation layer comprising a plurality of active contacts of a first type and a plurality of active contacts of a second type;

a patterned hard mask layer arranged on the isolation layer to selectively expose the plurality of active contacts of the first type to terminals of semiconductor devices of a semiconductor substrate, wherein the patterned hard mask layer selectively insulates the plurality of active contacts of the second type; and

a conductive material directly contacting the patterned hard mask layer and directly contacting the exposed plurality of active contacts of the first type, the conductive material arranged to couple the exposed plurality of active contacts of the first type to each other over an active area of the semiconductor devices.

2. The device of claim 1, in which a thickness of the patterned hard mask layer allows the conductive material to be conformally deposited on the exposed plurality of active contacts of the first type.

3. The device of claim 1, in which the conductive material is tungsten or copper.

4. The device of claim 1, in which the exposed plurality of active contacts of the first type comprises source contacts, drain contacts, or gate contacts.

5. The device of claim 1, in which the exposed plurality of active contacts of the first type comprises metal contacts or polysilicon contacts.

6. The device of claim 1, in which an insulated active contact of the second type and an exposed active contact of the first type are adjacent to each other.

7. The device of claim 1, in which the patterned hard mask layer creates rectangular openings to selectively expose the plurality of active contacts of the first type.

8. The device of claim 1, in which the conductive material directly contacting the exposed plurality of active contacts of the first type extends across unexposed ones of the plurality of active contacts of the second type.

9. The device of claim 1 integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.

10. A device including middle-of-line (MOL) layers, the MOL layers comprising:

an isolation layer comprising a plurality of active contacts of a first type and a plurality of active contacts of a second type;

means for selectively exposing the plurality of active contacts of the first type to terminals of semiconductor devices of a semiconductor substrate and for selectively insulating the plurality of active contacts of the second type; and

means for directly contacting the exposed plurality of active contacts of the first type to couple the exposed plurality of active contacts of the first type to each other.

11. The device of claim 10, in which the directly contacting means extends across unexposed ones of the plurality of active contacts of the second type.

12. The device of claim 10, in which a thickness of the exposing means allows the directly contacting means to be conformally deposited on the exposed plurality of active contacts of the first type.

13. The device of claim 10, in which the exposed plurality of active contacts of the first type comprises source contacts, drain contacts, or gate contacts.

14. The device of claim 10, in which the exposed plurality of active contacts of the first type comprises metal contacts or polysilicon contacts.

15. The device of claim 10, in which an insulated active contact of the second type and an exposed active contact of the first type are adjacent to each other.

16. The device of claim 10, integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit.