Processes used in fabricating a metal-insulator-semiconductor field effect transistor

• US 9,508,596 B2
• Filed: 06/20/2014
• Issued: 11/29/2016
• Est. Priority Date: 06/20/2014
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Tipirneni, Naveen, Pattanayak, Deva
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US14/311,165
• Publication Number:
  US 20150372077A1
• Time in Patent Office: 893 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

During fabrication, a second oxide layer is disposed over a first region and a second region of a structure. The second region includes a first oxide layer between the second oxide layer and an epitaxial layer. The first region corresponds to an active region of a metal-insulator-semiconductor field effect transistor (MISFET), and a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in the first region. The second region corresponds to a termination region of the MISFET. A mask is formed over the second region, and parts of the second oxide layer and the first oxide layer that are exposed through the gaps are removed, thereby exposing the epitaxial layer. Second-type dopant is deposited into the epitaxial layer through the resultant openings in the first and second oxide layers, thereby forming field rings for the MISFET.

Claims

1. A process used in fabricating a metal-insulator-semiconductor field-effect transistor (MISFET), said process comprising:

depositing a second oxide layer over a first region and a second region of a structure, said second region comprising a first oxide layer between said second oxide layer and an epitaxial layer, said first region having formed therein a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region, said first region corresponding to an active region of said MISFET and said second region corresponding to a termination region of said MISFET;

forming a mask over said second region, said mask comprising a first plurality of mask elements separated by gaps, said mask further comprising a second plurality of mask elements over said first region, said mask elements in said second plurality separated by a gap;

removing parts of said second oxide layer and said first oxide layer in said second region that are exposed through said gaps in said first plurality of mask elements, thereby exposing said epitaxial layer, and removing parts of said second oxide layer and said first-type dopant source region in said first region that are exposed through said gap in said second plurality of mask elements, thereby exposing said second-type dopant implant region;

depositing second-type dopant into said epitaxial layer through openings formed in said second region by said removing parts of said second oxide layer and said first oxide layer in said second region, thereby forming field rings for said MISFET;

forming a metal layer in contact with said first-type dopant source region and said second-type dopant implant region in said first region; and

forming a passivation layer over said first and second regions, said passivation layer extending into said openings in said second region formed by said removing parts of said second oxide layer and said first oxide layer in said second region.

2. The process of claim 1, wherein said forming said metal layer comprises:

depositing metal over said first and second regions after said exposing said second-type dopant implant region;

forming a second mask over said metal; and

removing said metal from areas around said second mask to form said metal layer in contact with said first-type dopant source region and said second-type dopant implant region.

3. The process of claim 1, further comprising, prior to said depositing said second oxide layer:

depositing a polysilicon layer over at least said first region;

removing a portion of said polysilicon layer to expose an area of said first region in which said first-type dopant source region, said second-type dopant body region, and said second-type dopant implant region are subsequently formed; and

after forming said first-type dopant source region and said second-type dopant body region, and before forming said second-type dopant implant region, forming a spacer in contact with a remaining portion of said polysilicon layer and also in contact with said first-type dopant source region.

4. The process of claim 1, wherein said gaps are uniformly sized and uniformly spaced.

5. The process of claim 1, wherein each of said gaps is between approximately 0.5 and 0.8 microns in width, and wherein each of said mask elements has a width of approximately 1.8 microns.

6. The MISFET fabricated by the process of claim 1.

7. A method for fabricating a metal-insulator-semiconductor field-effect transistor (MISFET), said method comprising:

depositing a first oxide layer over an epitaxial layer of a structure;

forming a first mask over said first oxide layer, said first mask defining a second region corresponding to a termination region of said MISFET, said first oxide layer removed from around said first mask to define a first region corresponding to an active region of said MISFET;

after removing said first mask, depositing a polysilicon layer over said first region and said second region;

forming a second mask over said polysilicon layer, said polysilicon layer removed from around said second mask to form an opening in said polysilicon layer in said first region, thereby exposing said epitaxial layer, wherein a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in said epitaxial layer through said opening;

after said second mask is removed, depositing a second oxide layer over said first region and said second region;

forming a third mask over said second region, said third mask comprising a first plurality of mask elements separated by gaps, wherein parts of said second oxide layer and said first oxide layer that are exposed through said gaps are removed, thereby exposing said epitaxial layer, wherein further second-type dopant is deposited into said epitaxial layer through openings formed by removing said parts of said second oxide layer and said first oxide layer, thereby forming field rings for said MISFET;

after said third mask is removed, depositing a metal layer over said first region and said second region;

forming a fourth mask over said metal layer, said metal layer removed from areas around said fourth mask;

after said fourth mask is removed, depositing a passivation layer over said first region and said second region; and

forming a fifth mask over said passivation layer, said passivation layer removed from around said fifth mask to form source and gate bond pad regions for said MISFET.

8. The method of claim 7, wherein said third mask further comprises a second plurality of mask elements over said first region, said mask elements in said second plurality separated by a gap, said method further comprising removing parts of said second oxide layer and said first-type dopant source region that are exposed through said gap, thereby also exposing said second-type dopant implant region.

9. The method of claim 7, further comprising, after forming said first-type dopant source region and said second-type dopant body region, and before forming said second-type dopant implant region, forming spacers on each side of said opening, said spacers in contact with a remaining portion of said polysilicon layer and also in contact with said first-type dopant source region.

10. The method of claim 7, wherein said gaps in said third mask are uniformly sized and uniformly spaced.

11. The method of claim 7, wherein each of said gaps in said third mask is between approximately 0.5 and 0.8 microns in width, and wherein each of said mask elements has a width of approximately 1.8 microns.

12. The MISFET fabricated by the process of claim 7.

13. A method for fabricating a metal-insulator-semiconductor field-effect transistor (MISFET), said method comprising:

removing a first oxide layer of a structure from around a first mask to define a first region corresponding to an active region of said MISFET and to expose an epitaxial layer underlying said first oxide layer, said first mask covering a second region corresponding to a termination region of said MISFET;

after removing said first mask and depositing a polysilicon layer over said first and second regions, removing said polysilicon layer from an area in said first region that is not covered by a second mask, thereby forming an opening in said polysilicon layer and exposing said epitaxial layer, wherein a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in said epitaxial layer through said opening;

after removing said second mask and depositing a second oxide layer over said first and second regions, removing said first oxide layer and said second oxide layer from areas in said second region that are exposed through gaps in a third mask, thereby exposing said epitaxial layer in said second region, wherein further second-type dopant is deposited into said epitaxial layer in said second region through openings formed by said removing said first oxide layer and said second oxide layer from areas in said second region, thereby forming field rings for said MISFET;

after removing said third mask and depositing a metal layer over said first and second regions, removing said metal layer from around a fourth mask; and

after removing said fourth mask and depositing a passivation layer over said first and second regions, removing said passivation layer from around a fifth mask to form source and gate bond pad regions for said MISFET.

14. The method of claim 13, further comprising removing parts of said second oxide layer and said first-type dopant source region that are exposed through a gap in said third mask over said first region, thereby also exposing said second-type dopant implant region.

15. The method of claim 13, further comprising, after forming said first-type dopant source region and said second-type dopant body region, and before forming said second-type dopant implant region, forming spacers on each side of said opening, said spacers in contact with a remaining portion of said polysilicon layer and also in contact with said first-type dopant source region.

16. The method of claim 13, wherein said gaps in said third mask are uniformly sized and uniformly spaced.

17. The method of claim 13, wherein each of said gaps in said third mask is between approximately 0.5 and 0.8 microns in width, and wherein each of said mask elements has a width of approximately 1.8 microns.

18. The MISFET fabricated by the process of claim 13.