Methods of making a monolithic microwave integrated circuit

• US 9,508,599 B2
• Filed: 04/22/2015
• Issued: 11/29/2016
• Est. Priority Date: 08/12/2010
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Sanders, Paul W., Burger, Wayne R., Dao, Thuy B., Keys, Joel E., Petras, Michael F., Pryor, Robert A., Ren, Xiaowei
• Primary Examiner(s): Nicely, Joseph C
• Application Number:
  US14/693,781
• Publication Number:
  US 20150228545A1
• Time in Patent Office: 587 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2223/6683 for monolithic microwave integrated circuit [MMIC]
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/40 : Capacitors
• CPC Class Codes: H01L 29/7816 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H03F 3/195 : in integrated circuits

Abstract

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face (63) of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC previously unobtainable.

Claims

1. A method for forming a monolithic microwave integrated circuit having an input terminal, an output terminal and a reference terminal, the method comprising:

providing a high resistivity initial semiconductor substrate having an initial thickness between a first surface and an initial second surface, and having a bulk resistivity equal to or greater than 100 Ohm-cm;

forming at least one transistor in and over the initial semiconductor substrate, wherein the at least one transistor has a control terminal, an output terminal, and a source region proximate the first surface;

forming a dielectric layer over the first surface and overlying the source region;

forming one or more conductor filled substrate vias extending through the dielectric layer and into the initial semiconductor substrate through the first surface;

forming an interlayer via in the dielectric layer;

forming electrical interconnections overlying the front surface of the semiconductor substrate to electrically couple the interlayer via with at least some of the multiple conductor filled substrate vias so that at least one of the substrate vias is electrically coupled to the source region of the transistor through the interlayer via and at least one of the electrical interconnections;

forming one or more planar capacitors over the first surface of the initial substrate, each capacitor having first and second terminals;

forming one or more planar inductors over the first surface of the initial substrate, wherein the first terminal or the second terminal of the one or more planar capacitors is coupled to a first terminal or a second terminal of the one or more planar inductors wherein other terminals of the one or more planar inductors are coupled to the substrate vias, to one or more terminals of the transistor or to one or more terminals of the microwave integrated circuit;

reducing the initial thickness, thereby creating a new rear surface of a thinned substrate on which inner ends of the substrate vias are exposed; and

applying a conductor to the new rear surface of the thinned substrate so that the exposed inner ends of the substrate vias are electrically connected to the conductor, and so that the source region is electrically connected to the conductor through the interlayer via, at least one of the electrical interconnections, and at least one of the substrate vias.

2. The method of claim 1, wherein:

the step of forming one or more planar capacitors comprises, forming first and second planar capacitors over the first surface of the initial substrate, each capacitor having first and second terminals; and

the step of forming one or more planar inductors comprises, forming first and second planar inductors over the first surface, each inductor having first and second terminals; and

wherein the first terminal of the first capacitor is coupled to the first terminal of the first inductor and the second terminal of the first inductor is coupled to the transistor input; and

wherein the first terminal of the second capacitor is coupled to the transistor output and the second terminal of the second capacitor is coupled to the first terminal of the second inductor; and

wherein the second terminal of the first capacitor, the second terminal of the second inductor and the reference terminal of the transistor are coupled to at least one of the conductor filled substrate vias.

3. The method of claim 1, wherein the initial substrate has a resistivity equal to or greater than 500 Ohm-cm.

4. The method of claim 1, wherein the initial substrate has a resistivity equal to or greater than 1000 Ohm-cm.

5. The method of claim 1, wherein the step of forming one or more planar inductors comprises, forming the inductors using copper, gold, silver or a combination thereof.

6. The method of claim 5, wherein the copper, gold, silver or combination thereof is at least 3 micrometers thick.

7. A method for forming a monolithic microwave integrated circuit, the method comprising:

forming portions of a transistor at a front surface of a semiconductor substrate, wherein the transistor has a doped common region, and wherein the semiconductor substrate has a bulk resistivity equal to or greater than 100 Ohm-cm;

forming multiple conductive through-substrate vias (TSVs) extending from the front surface of the semiconductor substrate at least partially through the semiconductor substrate;

forming electrical interconnections overlying the front surface of the semiconductor substrate to electrically couple the transistor with at least some of the multiple conductive TSVs; and

forming a reference node supported by a rear surface of the semiconductor substrate and electrically coupled with at least some of the multiple conductive TSVs.

8. The method of claim 7, wherein forming the electrical interconnections comprises:

forming a dielectric layer over the front surface of the semiconductor substrate and overlying the doped common region;

forming multiple interlayer conductive vias in the first dielectric layer and electrically coupled to the doped common region; and

forming one or more conductors overlying the front surface of the semiconductor substrate to electrically couple the multiple interlayer conductive vias with at least some of the multiple conductive TSVs.

9. The method of claim 7, wherein first ones of the multiple conductive TSVs couple the doped common region of the transistor to the reference node.

10. The method of claim 9, wherein second ones of the multiple conductive TSVs couple a first terminal of at least one capacitor that is monolithically formed over the semiconductor substrate to the reference node.

11. The method of claim 7, wherein:

the semiconductor substrate has an initial thickness between the front surface and a rear surface of the semiconductor substrate;

forming the multiple conductive TSVs includes forming the multiple conductive TSVs to extend from the front surface of the semiconductor substrate toward the rear surface and only partially through the semiconductor substrate;

wherein the method further includes, before forming the reference node, reducing the initial thickness of the semiconductor substrate by removing semiconductor material from the rear surface, thereby creating a new rear surface of a thinned substrate at which inner ends of the multiple conductive TSVs are exposed; and

wherein forming the reference node includes applying a conductor to the new rear surface of the thinned substrate so that the exposed inner ends of the multiple conductive TSVs are electrically connected to the conductor.

12. The method of claim 7, further comprising:

monolithically forming at least one passive component over the front surface of the semiconductor substrate.

13. The method of claim 12, wherein monolithically forming the at least one passive component comprises:

monolithically forming at least one capacitor over the front surface of the semiconductor substrate; and

monolithically forming at least one inductor over the front surface of the semiconductor substrate.

14. The method of claim 13, wherein the at least one capacitor is a planar capacitor, and wherein the at least one inductor is a planar inductor.

15. The method of claim 13, wherein:

monolithically forming the at least one capacitor includes forming two monolithic capacitors over the front surface of the semiconductor substrate, each having first and second terminals;

monolithically forming the at least one inductor includes forming two monolithic inductors over the front surface of the semiconductor substrate, each having first and second terminals;

wherein the first terminal of the first capacitor is coupled to the first terminal of the first inductor and the second terminal of the first capacitor is coupled to a first of the multiple conductive TSVs, and the second terminal of the first inductor is coupled to the doped common region of the transistor;

wherein the second capacitor and second inductor are serially coupled to form a combination, the combination having first and second terminals; and

wherein the first terminal of the combination is coupled to a doped output region of the transistor and the second terminal of the combination is coupled to a second of the multiple conductive TSVs.

16. A method for forming a monolithic microwave integrated circuit, the method comprising:

forming a Laterally-Diffused-Metal-Oxide-Semiconductor (LDMOS) transistor at a front surface of a semiconductor substrate, wherein the LDMOS transistor has a gate, a drain region, and a source region, and wherein the semiconductor substrate has a bulk resistivity equal to or greater than 100 Ohm-cm;

forming multiple conductive through-substrate vias (TSVs) extending from the front surface of the semiconductor substrate to a rear surface of the semiconductor substrate;

forming electrical interconnections overlying the front surface of the semiconductor substrate to electrically couple the transistor with at least some of the multiple conductive TSVs; and

forming a reference node supported by the rear surface of the semiconductor substrate and electrically coupled with at least some of the multiple conductive TSVs.

17. The method of claim 16, wherein the semiconductor substrate has a bulk resistivity equal to or greater than 500 Ohm-cm.

18. The method of claim 16, wherein the semiconductor substrate has a bulk resistivity equal to or greater than 1000 Ohm-cm.

19. The method of claim 16, wherein the semiconductor substrate substantially comprises float zone silicon.

20. A method for forming a monolithic microwave integrated circuit, the method comprising:

forming a transistor in a semiconductor substrate, wherein the transistor includes a doped common region;

forming a first dielectric layer over a front surface of the semiconductor substrate;

forming a first through-substrate via (“

TSV”

) extending through the first dielectric layer and the semiconductor substrate, wherein a region of the semiconductor substrate through which the first TSV passes has a bulk resistivity equal to or greater than 1000 Ohm-cm;

forming an interlayer via in the first dielectric layer, the first TSV electrically coupled to the doped common region of the transistor through the interlayer via;

monolithically forming a passive component over the front surface of the semiconductor substrate;

forming planar interconnections overlying the front surface of the semiconductor substrate and coupling the transistor and the passive component; and

forming a reference node supported by the rear surface of the semiconductor substrate, which is electrically coupled to the transistor through the first TSV.

21. The method of claim 20, further comprising:

forming a first metal layer over the dielectric layer, the first TSV extending through the first dielectric layer to the first metal layer.

22. The method of claim 20, wherein the transistor comprises a body contact region formed in the semiconductor substrate and having a dopant concentration less than the doped common region, the first TSV extending through the body contact region.