Semiconductor device including leadframe with a combination of leads and lands and method

• US 9,508,631 B1
• Filed: 12/30/2015
• Issued: 11/29/2016
• Est. Priority Date: 01/27/2011
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Bae, Jae Min, Kim, Byong Jin, Bang, Won Bae
• Primary Examiner(s): Kraig, William F
• Assistant Examiner(s): Chin, Edward
• Application Number:
  US14/983,937
• Time in Patent Office: 335 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49544 Deformation absorbing parts in the lead frame plane, e.g. meanderline shape H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/85 using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/18301 being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In one embodiment, a semiconductor device includes a die pad defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads and lands which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads and lands. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the lands being exposed in a common exterior surface of the package body.

Claims

1. A semiconductor device, comprising:

a generally planar die pad defining multiple peripheral edge segments;

a plurality of first lands segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto, wherein each of the first lands has a first land first top recessed portion disposed on a first land first end distal to the die pad;

a plurality of second lands segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto, wherein each of the second lands has a second land first top recessed portion disposed on a second land first end proximate to the die pad;

a plurality of third lands segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto, wherein each of the third lands has a third land first bottom recessed portion disposed on a third land first end distal to the die pad;

a semiconductor die attached to the die pad and electrically connected to the first, second, and third lands; and

a package body defining a generally planar bottom surface and a side surface, the package body at least partially encapsulating the first, second, and third lands and the semiconductor die such that at least portions of the first, second, and third lands are exposed in and substantially flush with the bottom surface of the package body, and are positioned between the die pad and the side surface of the package body, wherein the first land first recessed portion of each first land, the second land first top recessed portion of each second land, and the third land first bottom recessed portion of each third land are encapsulated by the package body.

2. The semiconductor device of claim 1, wherein each of the first lands has a first land second top recessed portion disposed on a first land second end proximate to the die pad.

3. The semiconductor device of claim 1, wherein each of the third lands has a third land second bottom recessed portion disposed on a third land second end proximate to the die pad.

4. The semiconductor device of claim 1 further comprising a tie bar comprising an inner portion and an outer portion separated from the inner portion by a gap, the inner portion attached to and extending from the die pad, the tie bar having a tie bar top surface and a tie bar bottom surface, wherein the tie bar top surface of the outer portion is co-planar with the die pad top surface, and wherein a first portion of the tie bar bottom surface of the outer portion comprises a recessed surface that is half-etched, wherein the first portion of the tie bar bottom surface is encapsulated by the package body.

5. The semiconductor device of claim 4, wherein the die pad has a generally quadrangular configuration, and the first, second, and third lands are segregated into at least four sets which each extend along a respective one of the peripheral edge segments of the die pad.

6. The semiconductor device of claim 5, wherein the first lands are generally concentrically positioned between the second lands and the die pad such that each set of the first lands extends along a corresponding set of the second lands, and the second lands are generally concentrically positioned between the third lands and the first lands such that each set of the second lands extends along a corresponding set of the third lands, and wherein a second portion of the tie bar bottom surface is co-planar with the die pad bottom surface and exposed in and substantially flush with the bottom surface of the package body.

7. The semiconductor device of claim 6, wherein the first lands of each set thereof are offset relative to the second lands of the corresponding set thereof.

8. The semiconductor device of claim 1, wherein a portion of the die pad is exposed in and substantially flush with the bottom surface of the package body.

9. The semiconductor device of claim 1, wherein the first lands are separated from the second lands by at least one trench formed in the bottom surface of the package body.

10. The semiconductor device of claim 1, wherein the semiconductor die is electrically connected to the first, second, and third lands by conductive wires which are covered by the package body.

11. The semiconductor device of claim 1 further comprising a plurality of fourth lands segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto, wherein each of the fourth lands has a fourth land first bottom recessed portion disposed on a fourth land first end distal to the die pad, wherein the fourth lands are generally concentrically positioned between the second lands and the third lands.

12. The semiconductor device of claim 11, wherein each of the fourth lands has a fourth land second bottom recessed portion disposed on fourth land second end proximate to the die pad.

13. A semiconductor device, comprising:

a generally planar die pad;

a plurality of first lands extending along peripheral edge segments of the die pad in spaced relation thereto, wherein each of the first lands has a first land first top recessed portion disposed on a first land first end distal to the die pad;

a plurality of second lands extending along peripheral edge segments of the die pad in spaced relation thereto, wherein each of the second lands has a second land first top recessed portion disposed on a second land first end proximate to the die pad;

a plurality of third lands extending along peripheral edge segments of the die pad in spaced relation thereto, wherein each of the third lands has a third land first bottom recessed portion disposed on a third land first end distal to the die pad;

a semiconductor die attached to the die pad and electrically coupled to the first, second, and third lands; and

a package body defining a generally planar bottom surface and a side surface, the package body at least partially encapsulating the first, second, and third lands and the semiconductor die such that at least portions of the first, second, and third lands are exposed in the bottom surface of the package body, and are positioned between the die pad and the side surface of the package body, wherein the first land first recessed portion of each first land, the second land first top recessed portion of each second land, and the third land first bottom recessed portion of each third land are encapsulated by the package body.

14. The semiconductor device of claim 13 further comprising:

a tie bar comprising an inner linear portion and an outer linear portion separated from the inner linear portion by a gap, the inner linear portion attached to and extending from the die pad, wherein the outer linear portion has a bottom surface with a first portion that is generally co-planar to a bottom surface of the die pad and a second portion that is recessed such that the second portion is recessed relative to the first portion, and wherein the second portion of the bottom surface of the tie bar is encapsulated by the package body.

15. The semiconductor device of claim 13, wherein the first lands are generally concentrically positioned between the second lands and the die pad, and the second lands are generally concentrically positioned between the third lands and the first lands.

16. The semiconductor device of claim 15, wherein:

each of the first lands has a first land second top recessed portion disposed on a first land second end proximate to the die pad; and

each of the third lands has a third land second bottom recessed portion disposed on a third land second end proximate to the die pad.

17. The semiconductor device of claim 16 further comprising a plurality of fourth lands extending along peripheral edge segments of the die pad in spaced relation thereto, wherein each of the fourth lands has a fourth land first bottom recessed portion disposed on a fourth land first end distal to the die pad, wherein the fourth lands are generally concentrically positioned between the second lands and the third lands.

18. The semiconductor device of claim 17, wherein each of the fourth lands has a fourth land second bottom recessed portion disposed on fourth land second end proximate to the die pad.

19. The semiconductor device of claim 18, wherein:

the plurality of first lands and the plurality of second are offset relative to each other; and

the plurality of third lands and the plurality of fourth lands are offset relative to each other.

20. A semiconductor device, comprising:

a die pad defining multiple peripheral edge segments, a die pad top surface and a die pad bottom surface;

a plurality of first lands segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto;

a plurality of second lands segregated into at least two sets that extend along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto, wherein at least one set of first lands is segregated into a first group and a second group, and wherein the first lands in the first group and the first lands in the second group are each laterally separated by a first space having a first width, and wherein the first group is laterally separated from the second group by a second space having a second width greater than the first width;

a plurality of leads segregated into at least two sets that extend along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto, each of the leads defining at least one land portion;

a semiconductor die attached to the die pad and electrically connected to the first and second lands and the leads; and

a package body defining a generally planar bottom surface and a side surface, the package body at least partially encapsulating the first and second lands, the leads, and the semiconductor die such that at least portions of the first and second lands and the land portions of the leads are exposed in and substantially flush with the bottom surface of the package body, and are positioned between the die pad and the side surface of the package body.