Semiconductor package

• US 9,508,657 B2
• Filed: 04/28/2015
• Issued: 11/29/2016
• Est. Priority Date: 06/26/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Seok-Hyun
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US14/698,353
• Publication Number:
  US 20150380361A1
• Time in Patent Office: 581 Days
• Field of Search: 257/659
• US Class Current: 1/1
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15156 : Side view
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor device is provided. The semiconductor includes a semiconductor chip, a package substrate, and an electromagnetic interference (EMI) shielding layer. The package substrate, arranged under the semiconductor chip, is electrically connected to the semiconductor chip. The package substrate has a receiving groove. The EMI shielding layer is arranged in the receiving groove to shield EMI propagated from a lower surface of the semiconductor chip through the package substrate.

Claims

1. A semiconductor package comprising:

a semiconductor chip;

a package substrate arranged under the semiconductor chip and electrically connected to the semiconductor chip, the package substrate having a receiving groove; and

an electromagnetic interference (EMI) shielding layer arranged in the receiving groove to shield EMI propagated from a lower surface of the semiconductor chip through the package substrate,

wherein the package substrate comprises a central portion and a peripheral portion, and the central portion is upwardly protruded from the peripheral portion to form the receiving groove.

2. The semiconductor package of claim 1, wherein the EMI shielding layer has a lower surface substantially coplanar with a lower surface of the peripheral portion of the package substrate.

3. The semiconductor package of claim 1, wherein the EMI shielding layer has an upper surface substantially coplanar with an upper surface of the peripheral portion of the package substrate.

4. The semiconductor package of claim 1,

wherein the package substrate further comprises a ground line which is electrically connected to the EMI shielding layer.

5. The semiconductor package of claim 4,

wherein the package substrate further comprises an auxiliary EMI shielding layer through which the EMI shielding layer is connected to the ground line.

6. The semiconductor package of claim 1, further comprising an EMI shielding can covering the package substrate and the semiconductor chip to shield EMI propagated from an upper surface and side surfaces of the semiconductor chip.

7. The semiconductor package of claim 6,

wherein the package substrate further comprises a ground line, and

wherein the EMI shielding can is electrically connected to the ground line.

8. The semiconductor package of claim 1,

wherein the package substrate comprises a flexible substrate.

9. The semiconductor package of claim 1,

wherein the EMI shielding layer comprises an alloy of nickel and iron, an alloy of copper and nickel or silver.

10. A semiconductor package comprising:

a semiconductor chip;

a package substrate arranged under the semiconductor chip and electrically connected to the semiconductor chip, the package substrate having a protrusion protruded toward the semiconductor chip to form a receiving groove;

an EMI shielding can covering the package substrate and the semiconductor chip to shield EMI propagated from an upper surface and side surfaces of the semiconductor chip; and

an EMI shielding layer arranged in the receiving groove to shield EMI propagated from a lower surface of the semiconductor chip through the package substrate.

11. The semiconductor package of claim 10,

wherein the package substrate further comprises a ground line which is connected to the EMI shielding layer and the EMI shielding can.

12. The semiconductor package of claim 11,

wherein the protrusion is positioned in a central portion of the package substrate, and

wherein the EMI shielding layer comprises a lower surface substantially coplanar with a lower surface of the peripheral portion of the package substrate.

13. The semiconductor package of claim 12, further comprising an auxiliary EMI shielding layer arranged in a peripheral portion of the package substrate to electrically connect the EMI shielding layer and the ground line.