Electrical connector between die pad and z-interconnect for stacked die assemblies

• US 9,508,689 B2
• Filed: 09/30/2015
• Issued: 11/29/2016
• Est. Priority Date: 05/20/2008
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Co, Reynaldo, Leal, Jeffrey S., Pangrle, Suzette K., McGrath, Scott, Melcher, De Ann Eileen, Barrie, Keith L., Villavicencio, Grant, Del Rosario, Elmer M., Bray, John R.
• Primary Examiner(s): SUN, YU-HSI DAVID
• Application Number:
  US14/871,185
• Publication Number:
  US 20160027761A1
• Time in Patent Office: 426 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68336 involving stretching of the auxiliary support post dicing
• CPC Class Codes: H01L 2224/0235 Shape of the redistribution layers
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03318 by dispensing droplets
• CPC Class Codes: H01L 2224/0332 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/03632 Ablation by means of a laser or focused ion beam [FIB]
• CPC Class Codes: H01L 2224/03848 Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/05016 in side view
• CPC Class Codes: H01L 2224/05017 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/0529 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/76155 : Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82102 : using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06551 : Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3185 : the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

Claims

1. A method for forming a connector on a die pad at a wafer level of processing, comprising

forming a channel defining an interconnect die edge of a first die of the wafer and an adjacent edge of a second die of the wafer, wherein the interconnect die edge of the first die, the edge of the second die, and the channel therebetween have longest dimensions extending in a first direction, and a width of the channel extends in a second direction from the interconnect die edge to the adjacent edge of the second die;

forming an electrically insulative material overlying a front surface of the wafer, the interconnect die edge, and the edge of the second die, the insulative material spanning an entire width of the channel;

forming spots of a curable electrically conductive material over die pads and extending over an interconnect die edge above the channel;

curing the conductive material; and

in a wafer cutting procedure thereafter severing the spots.

2. The method of claim 1, wherein the electrically insulative material is formed such that the die pads are exposed within openings in the electrically insulative material.

3. The method of claim 1, wherein the spots are formed so as to span the entire width of the channel.

4. The method of claim 1, wherein the spots are formed such that the spots do not span the entire width of the channel.

5. The method of claim 1, such that the severed spots overhang the interconnect die edge.

6. The method of claim 1, wherein the channel is a first channel, and the wafer cutting procedure forms a second channel which is narrower than the first channel.

7. The method of claim 1, further comprising thinning the wafer subsequent to forming the channel.

8. The method of claim 7, wherein the channel is formed to a depth greater than an eventual thickness of the die and less than a full wafer thickness prior to the thinning.

9. The method of claim 7, further comprising applying a die attach film to the wafer after the thinning.

10. The method of claim 9, further comprising cutting through the spots and die attach film.

11. A method for preparing a die for stacking and electrical connection, comprising:

performing a first wafer cutting procedure along first saw streets, thereby forming channels defining interconnect die edges of first die and adjacent edges of second die of a wafer, wherein each interconnect die edge, each adjacent edge of the second die, and each channel therebetween has a longest dimension extending in a first direction, and a width of each channel extends in a second direction from the interconnect die edge of a first die to the adjacent edge of a second die;

forming an electrically insulative material overlying a front surface of the wafer, the interconnect die edges, and the adjacent edges of the second die adjacent thereto, the insulative material spanning an entire width of each channel;

forming spots of an electrically conductive material over die pads and extending in a direction parallel to a front surface of the wafer beyond an interconnect die edge; and

in a second wafer cutting procedure thereafter severing the spots.

12. The method of claim 11 wherein the second wafer cutting procedure forms narrower channels than the first wafer cutting procedure.

13. The method of claim 11, further comprising thinning the wafer subsequent to carrying out the first wafer cutting procedure.

14. The method of claim 11 wherein the first wafer cutting procedure is made to a depth greater than the eventual die thickness and less than the full wafer thickness, forming interconnect sidewalls.

15. The method of claim 11, wherein the spots bridge the channel prior to being severed, and after being severed the spots include overhang portions extending beyond the interconnect die edge.

16. The method of claim 11, wherein the severed spots include overhang portions extending beyond a surface of the electrically insulative material.

17. The method of claim 11, wherein the spots are formed such that the spots do not span the entire width of the channel.

18. The method of claim 11, such that the severed spots overhang the interconnect die edge.