Flipped die stacks with multiple rows of leadframe interconnects

• US 9,508,691 B1
• Filed: 12/16/2015
• Issued: 11/29/2016
• Est. Priority Date: 12/16/2015
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Delacruz, Javier A., Haba, Belgacem, Vu, Tu Tam, Katkar, Rajesh
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US14/971,384
• Time in Patent Office: 349 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29191 The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48011 Length
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/49051 Connectors having different shapes
• CPC Class Codes: H01L 2224/4909 Loop shape arrangement
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49173 Radial fan-out arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/8385 : using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/85181 : connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
• CPC Class Codes: H01L 2224/85186 : connecting first outside the semiconductor or solid-state body, i.e. off-chip, reverse stitch
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49551 : characterised by bent parts
• CPC Class Codes: H01L 23/49555 : the bent parts being the outer leads
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/06 : Polymers
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07025 : Polyimide
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

Stacked microelectronic packages comprise microelectronic elements each having a contact-bearing front surface and edge surfaces extending away therefrom, and a dielectric encapsulation region contacting an edge surface. The encapsulation defines first and second major surfaces of the package and a remote surface between the major surfaces. Package contacts at the remote surface include a first set of contacts at positions closer to the first major surface than a second set of contacts, which instead are at positions closer to the second major surface. The packages are configured such that major surfaces of each package can be oriented in a nonparallel direction with the major surface of a substrate, the package contacts electrically coupled to corresponding contacts at the substrate surface. The package stacking and orientation can provide increased packing density.

Claims

1. A stacked microelectronic assembly, comprising:

a plurality of stacked encapsulated microelectronic packages, each encapsulated microelectronic package comprising;

a microelectronic element having a front surface defining a plane, a plurality of edge surfaces extending away from the plane of the front surface, the microelectronic element having a plurality of chip contacts at the front surface;

each package having a plurality of remote surfaces, and an encapsulation region contacting at least one edge surface of the microelectronic element and extending away from the at least one edge surface to a corresponding one of the remote surfaces, the encapsulation region having first and second oppositely-facing major surfaces, each major surface substantially parallel to the plane of the microelectronic element; and

a plurality of first electrically conductive package contacts disposed within a first plane parallel to the first major surface and a plurality of second electrically conductive package contacts disposed within a second plane parallel to the first plane and displaced from the first package contacts, the first package contacts and the second package contacts being disposed at a single one of the remote surfaces, the chip contacts electrically coupled with the package contacts,

the plurality of microelectronic packages stacked one above another in the stacked assembly such that the planes of the microelectronic elements in each of the plurality of microelectronic packages are parallel with one another.

2. The stacked microelectronic assembly as claimed in claim 1, wherein the first package contacts and the second package contacts of each package in the stacked assembly face and are electrically coupled with corresponding substrate contacts at a major surface of a substrate external to the encapsulation regions of each package of the stacked assembly, the major surface oriented non-parallel with the planes of the microelectronic elements in the stacked assembly.

3. The stacked microelectronic assembly as claimed in claim 2, wherein the packages are stacked such that the first major surface of each next higher ordered package faces the second major surface of the next lower ordered package adjacent thereto, wherein a plurality of pairs of first and second package contacts are aligned and electrically coupled with one another, each pair comprising a first package contact of each next higher ordered package and the second package contact of the next lower ordered package aligned and electrically coupled therewith.

4. The stacked microelectronic assembly as claimed in claim 3, wherein each of the first package contacts and the second package contacts of each package is a portion of a first leadframe element or a portion of a second leadframe element, respectively, of a common leadframe, the second leadframe elements having first portions interdigitated among neighboring first leadframe elements, the second package contacts being remote from the first portions and remote from the first leadframe elements.

5. The stacked microelectronic assembly as claimed in claim 4, wherein the second leadframe elements of at least one of the packages have bends between the first portions and the second package contacts.

6. The stacked microelectronic assembly as claimed in claim 4, wherein the packages comprise first packages each having a first orientation, and second packages having a second orientation opposite from the first orientation, wherein each of the first packages and the second packages has an identical arrangement of the first package contacts and the second package contacts thereon, wherein at least some of the first packages are stacked immediately adjacent with at least some of the second packages among the stacked packages.

7. The stacked microelectronic assembly as claimed in claim 2, wherein the substrate contacts comprise a plurality of sets of substrate contacts, each set comprising a plurality of the first substrate contacts joined with the first package contacts of only one of the microelectronic packages via an electrically conductive bonding material, and a plurality of second substrate contacts joined with the second package contacts of only the one microelectronic package via an electrically conductive bonding material.

8. The stacked microelectronic assembly as claimed in claim 7, wherein the common leadframe of at least one of the packages further comprises a die attach pad, wherein the microelectronic element has a face bonded to the die attach pad.

9. The stacked microelectronic assembly as claimed in claim 8, wherein at least one of the packages includes a first microelectronic element, the face of the first microelectronic element bonded to a first surface of the die attach pad, and includes a second microelectronic element, the face of the second microelectronic element bonded to a second surface of the die attach pad opposite from the first surface.

10. The stacked microelectronic assembly as claimed in claim 9, wherein the at least one package includes a plurality of first stacked microelectronic elements including the first microelectronic element, each first stacked microelectronic element overlying the first surface and electrically coupled with at least one of the first or second package contacts, and includes a plurality of second stacked microelectronic elements including the second microelectronic element, each second stacked microelectronic element overlying the second surface and electrically coupled with at least one of the first or second package contacts.

11. The stacked microelectronic assembly as claimed in claim 1, further comprising third package contacts, wherein the first package contacts, the second package contacts and the third package contacts are portions of first leadframe elements, second leadframe elements, and third leadframe elements, respectively, wherein immediately adjacent package contacts are spaced apart from one another in a direction orthogonal to the major surfaces of the package and the first package contacts are spaced farther apart in the orthogonal direction from the third package contacts than from the second package contacts.

12. An encapsulated microelectronic package, comprising:

a microelectronic element having a front surface defining a plane, a plurality of edge surfaces extending away from the plane of the front surface, and a plurality of chip contacts at the front surface;

the package having a plurality of remote surfaces, and an encapsulation region contacting at least one edge surface of the microelectronic element and extending away from the at least one edge surface to a corresponding one of the remote surfaces, the encapsulation region having first and second oppositely-facing major surfaces, each major surface being at least substantially parallel to the plane of the microelectronic element; and

a plurality of first electrically conductive package contacts disposed within a first plane parallel to the first major surface and a plurality of second electrically conductive package contacts disposed within a second plane parallel to the second and displaced from the first package contacts major surface, the first package contacts and the second package contacts being disposed at a single one of the remote surfaces, the chip contacts electrically coupled with the package contacts.

13. The microelectronic package as claimed in claim 12, wherein each of the first package contacts and the second package contacts of each package is a portion of a first leadframe element or a portion of a second leadframe element, respectively, of a common leadframe, the second leadframe elements having first portions interdigitated among neighboring first leadframe elements, the second package contacts being remote from the first portions and remote from the first leadframe elements.

14. The microelectronic package as claimed in claim 13, wherein the second leadframe elements of at least one of the packages have bends between the first portions and the second package contacts.

15. The microelectronic package as claimed in claim 13, wherein the common leadframe further comprises a die attach pad, wherein the microelectronic element has a face bonded to the die attach pad.

16. The microelectronic package as claimed in claim 15, wherein the microelectronic element is a first microelectronic element, the face of the first microelectronic element facing toward a first surface of the die attach pad, the package further comprising a second microelectronic element, the face of the second microelectronic element facing toward a second surface of the die attach pad opposite from the first surface.

17. The microelectronic package as claimed in claim 16, wherein the microelectronic element comprises a plurality of the first microelectronic elements stacked and overlying the first surface and electrically coupled with at least one of the first package contacts or second package contacts, and comprises a plurality of the second microelectronic elements stacked and overlying the second surface and electrically coupled with at least one of the first package contacts or the second package contacts.

18. The microelectronic package as claimed in claim 17, wherein the plurality of first stacked microelectronic elements are stacked such that an edge surface of each first stacked microelectronic element is offset in a direction perpendicular to the edge surface from the edge surface of each first stacked microelectronic element which is immediately beneath such first stacked microelectronic element, and the plurality of first stacked microelectronic elements are electrically coupled with the first package contacts and the second package contacts via wire bonds.

19. The microelectronic package as claimed in claim 15, wherein the microelectronic element comprises first and second microelectronic elements, the faces of the first and second microelectronic elements overlying and mechanically coupled with a first surface of the die attach pad.

20. The microelectronic package as claimed in claim 13, further comprising third package contacts, wherein the first package contacts, the second package contacts and the third package contacts are end portions of first leadframe elements, second leadframe elements, and third leadframe elements, respectively, wherein immediately adjacent end portions are spaced apart from one another in a direction orthogonal to the major surfaces of the package and the first package contacts are spaced farther apart in the orthogonal direction from the third package contacts than from the second package contacts.

21. The microelectronic package as claimed in claim 13, wherein the first package contacts and the second package contacts do not extend more than 25 microns beyond a surface of the encapsulation region, the package further comprising a compliant material disposed between first leadframe elements and at least some of the second leadframe elements at locations proximate to said remote surface of the encapsulation.

22. The microelectronic package as claimed in claim 13, wherein the second leadframe elements protrude beyond a surface of the encapsulation region by more than 50 microns.