CMOS gate stack structures and processes

• US 9,508,728 B2
• Filed: 01/21/2016
• Issued: 11/29/2016
• Est. Priority Date: 06/06/2011
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Hoffmann, Thomas, Ranade, Pushkar, Thompson, Scott E.
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): Kilpatrick, Warren H
• Application Number:
  US15/003,151
• Publication Number:
  US 20160141292A1
• Time in Patent Office: 313 Days
• Field of Search: 257/369
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/18 Peripheral circuit regions

Abstract

A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.

Claims

1. A semiconductor device integrated circuit comprising:

a first device for SRAM comprising a first substantially undoped layer at a semiconductor surface, a first highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, a first well of the first conductivity type beneath the first highly doped screening layer and a first gate stack on the first substantially undoped layer,

a second device for SRAM comprising a second substantially undoped layer at the semiconductor surface, a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer, a second well of the second conductivity type beneath the second highly doped screening layer and a second gate stack on the second substantially undoped layer,

a third device for logic comprising a third substantially undoped layer at the semiconductor surface, a third highly doped screening layer of a first conductivity type beneath the third substantially undoped layer, a third well of the first conductivity type beneath the third highly doped screening layer and a third gate stack on the third substantially undoped layer,

a fourth device for logic comprising a fourth substantially undoped layer at the semiconductor surface, a fourth highly doped screening layer of a second conductivity type beneath the fourth substantially undoped layer, a fourth well of the second conductivity type beneath the fourth highly doped screening layer and a fourth gate stack on the fourth substantially undoped layer,

shallow trench isolation regions separating the first device, the second device, the third deice and the fourth device,

wherein each of the first gate stack, the second gate stack, the third gate stack and the fourth gate stack has a workfunction that is substantially midgap with respect to the semiconductor material.

2. The semiconductor device integrated circuit of claim 1, wherein the first gate stack comprises a first metal having a workfunction that is substantially midgap with respect to the semiconductor material.

3. The semiconductor device integrated circuit of claim 1, wherein at least one of the first gate stack and the second gate stack comprises a capping layer.

4. The semiconductor device integrated circuit of claim 2, wherein the second gate stack comprises a second metal having a workfunction that is substantially midgap with respect to the semiconductor material, wherein the workfunction of the first metal and the workfunction of the second metal are not equal in value.

5. The semiconductor device integrated circuit of claim 2, wherein each of the first gate stack, the second gate stack, the third gate stack and the fourth gate stack comprises a gate dielectric layer, at least one of the gate dielectric layer comprises a high-K dielectric layer, and wherein the first metal comprises at least one of TiN, TaN, WN, Al, Ti, or any alloys thereof.

6. The semiconductor device integrated circuit of claim 1, further comprising a layer of an alloy of silicon and germanium at the surface in at least one of the third active region and the fourth active region.

7. The semiconductor device integrated circuit of claim 1, further comprising a halo layer in the third active region and the fourth active region and not in the first active region or the second active region.