Thin film transistor array substrate

• US 9,508,747 B2
• Filed: 07/06/2015
• Issued: 11/29/2016
• Est. Priority Date: 04/30/2013
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Choi, Hee Dong
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US14/792,316
• Publication Number:
  US 20150311236A1
• Time in Patent Office: 512 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor array substrate is discussed. The thin film transistor array substrate includes, according to one embodiment, gate and data lines crossing each other, a gate insulation film, a gate electrode, an active layer, an etch stop layer formed on the active layer to define a channel region of the active layer, and a source electrode and a drain electrode formed on the active layer. The etch stop layer is between the source and drain electrodes spaced apart from the etch stop layer. The source electrode and the drain electrode include a first electrode layer and a second electrode layer disposed on the first electrode. The first electrode layer is formed from a dry-etchable material and the second electrode layer is formed from a wet-etchable material.

Claims

1. A thin film transistor array substrate comprising:

a gate line and a data line formed on a substrate, the gate and data lines crossing each other;

a gate insulation film formed between the gate and data lines;

a gate electrode formed at an intersection of the gate and data lines;

an active layer formed on the gate insulation film to overlap the gate electrode, wherein all of the active layer is flat;

an etch stop layer formed on the active layer to define a channel region of the active layer;

a source electrode and a drain electrode formed on the active layer to partially overlap the active layer,

wherein the etch stop layer is between the source and drain electrodes, and the source and drain electrodes are spaced apart from the etch stop layer,

each of the source electrode and the drain electrode includes a first electrode layer and a second electrode layer disposed on the first electrode layer,

each of the first electrode layers is formed from a dry-etchable material and each of the second electrode layers is formed from a wet-etchable material, and

each of the first and second electrode layers in each of the source and drain electrodes has three steps and is tilted between each of the steps; and

a passivation filmed form between both of the first and second electrode layers included in the source electrode and the etch stop layer, and formed between both of the first and second electrode layers included in the drain electrode and the etch stop layer,

wherein a top step of the first electrode layer included in each of the source and drain electrodes is directly on the active layer, and

the passivation film formed between both of the first and second electrode layers included in the source electrode and the etch stop layer is directly on the active layer, and the passivation film formed between both of the first and second electrode layers included in the drain electrode and the etch stop layer is directly on the active layer.

2. The thin film transistor array substrate of claim 1, wherein the source and drain electrodes do not overlap the gate electrode.

3. The thin film transistor array substrate of claim 1, wherein the active layer is formed only in a region over the gate electrode.

4. The thin film transistor array substrate of claim 1, wherein the source electrode is formed in a shape of U.

5. The thin film transistor array substrate of claim 4, wherein both ends of the source electrode do not overlap the gate electrode.

6. The thin film transistor array substrate of claim 4, wherein the source electrode is formed only in a region adjacent to the gate electrode.

7. The thin film transistor array substrate of claim 1, wherein the first and second electrode layers of the source electrode are sequentially stacked, and the first and second electrode layers of the drain electrode are sequentially stacked.

8. The thin film transistor array substrate of claim 1, wherein the source and drain electrodes and the etch stop layer are formed directly on the active layer.