Pixel unit and method of fabricating the same, array substrate and display device

• US 9,508,755 B2
• Filed: 11/28/2013
• Issued: 11/29/2016
• Est. Priority Date: 08/22/2013
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Kong, Xiangyong, Wang, Dongfang, Cheng, Jun, Sun, Hongda
• Primary Examiner(s): LUKE, DANIEL M
• Application Number:
  US14/361,700
• Publication Number:
  US 20150129881A1
• Time in Patent Office: 1,097 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

The present invention provides a pixel unit including a thin film transistor and a pixel electrode, the thin film transistor includes a gate, a source and a drain, and the pixel electrode is electrically connected to the drain through a via hole. An upper end surface of the via hole is connected to the pixel electrode, and a lower end surface of the via hole is connected to the drain. The via hole is a step-shaped hole, and an area of the upper end surface of the via hole is larger than that of the lower end surface of the via hole. The present invention also provides a method of fabricating the pixel unit, an array substrate including the pixel unit, and a display device including the array substrate.

Claims

1. A pixel unit, including a thin film transistor and a pixel electrode, the thin film transistor including a gate, a source and a drain, the pixel electrode being electrically connected to the drain through a via hole, wherein

a via-hole electrode is provided to fill the via hole, an upper end surface of the via-hole electrode is connected to a lower surface of the pixel electrode, and a lower end surface of the via-hole electrode is connected to the drain,

the via hole is a step-shaped hole, and an area of the upper end surface of the via-hole electrode is larger than that of the lower end surface of the via-hole electrode,

the via hole includes a large via portion and a small via portion, the via-hole electrode includes a large electrode portion corresponding to the large via portion and a small electrode portion corresponding to the small via portion, and

one end surface of the large electrode portion is connected to the pixel electrode, one end surface of the small electrode portion is connected to the drain, and a height of the large electrode portion along a vertical direction is the same as that of the small electrode portion.

2. The pixel unit according to claim 1, wherein

the thin film transistor further includes an organic insulation layer provided above the source and the drain of the thin film transistor, and the via hole penetrates the organic insulation layer.

3. The pixel unit according to claim 2, wherein

the thin film transistor further includes an inorganic insulation layer provided between the organic insulation layer and the source and drain of the thin film transistor, and the via hole penetrates the inorganic insulation layer.

4. The pixel unit according to claim 3, wherein

the large electrode portion and one part of the small electrode portion are provided in the organic insulation layer, and the other part of the small electrode portion is provided in the inorganic insulation layer.

5. The pixel unit according to claim 3, wherein

the organic insulation layer is made of a photosensitive resin, and an etching selectivity ratio between the inorganic insulation layer and the organic insulation layer is no less than 10.

6. The pixel unit according to claim 5, wherein

the inorganic insulation layer is a single-layer structure made of any one of silicon oxide, silicon nitride, hafnium oxide and aluminum oxide, or the inorganic insulation layer is a multi-layer structure made of any combination of silicon oxide, silicon nitride, hafnium oxide and aluminum oxide.

7. A method of fabricating a pixel unit, comprising:

forming a thin film transistor;

forming a via hole that penetrates an upper surface of the thin film transistor to reach a drain of the thin film transistor, the via hole being a step-shaped hole, an area of an upper end surface of the via hole being larger than that of a lower end surface of the via hole; and

forming a via-hole electrode that fills the via hole and forming a pixel electrode so that the pixel electrode is electrically connected to the drain through the via hole, wherein

an area of an upper end surface of the via-hole electrode is larger than that of a lower end surface of the via-hole electrode, the upper end surface of the via-hole electrode is connected to a lower surface of the pixel electrode and the lower end surface of the via-hole electrode is connected to the drain,

the via hole includes a large via portion and a small via portion, the via-hole electrode includes a large electrode portion corresponding to the large via portion and a small electrode portion corresponding to the small via portion, and

one end surface of the large electrode portion is connected to the pixel electrode, one end surface of the small electrode portion is connected to the drain, and a height of the large electrode portion along a vertical direction is the same as that of the small electrode portion.

8. The method according to claim 7, wherein

forming the thin film transistor comprises:

forming a source and a drain of the thin film transistor;

forming an inorganic insulation layer above the source and the drain; and

forming an organic insulation layer on the inorganic insulation layer.

9. The method according to claim 8, wherein

the organic insulation layer is made of a photosensitive resin material, and an etching selectivity ratio between the inorganic insulation layer and the organic insulation layer is no less than 10;

and

when forming the via hole, a first part corresponding to the small via portion of the thin film transistor is fully exposed, and a second part of the thin film transistor is half exposed, the second part surrounding the first part and being located at a part corresponding to the large via portion.

10. The method according to claim 9, wherein

forming the via hole comprises:

disposing a mask plate above the organic insulation layer and exposing the organic insulation layer, the mask plate including a non-transmissive region, a transmissive region and a semi-transmissive region, with the transmissive region corresponding to the small via portion and the semi-transmissive region corresponding to the large via portion; and

developing the organic insulation layer, and then etching the organic insulation layer subjected to development and etching the inorganic insulation layer, so as to form the via hole penetrating the organic insulation layer and the inorganic insulation layer.

11. The method according to claim 8, wherein

the organic insulation layer is made of a non-photosensitive resin material;

and

when forming the via hole, a first via penetrating the organic insulation layer and the inorganic insulation layer is formed by a patterning process, area of a cross section of the first via being the same as that of the small via portion, and after forming the first via, the large via portion is formed by a patterning process.

12. The method according to claim 7, wherein

the pixel electrode is formed by an inkjet printing process.

13. The method according to claim 12, further comprising:

performing an annealing process on the thin film transistor, with an annealing temperature in the range of 200°

C. to 600°

C. and an annealing holding time period in the range of 30 minutes to 3 hours.

14. An array substrate, including a pixel unit comprising a thin film transistor and a pixel electrode, the thin film transistor including a gate, a source and a drain, the pixel electrode being electrically connected to the drain through a via hole, wherein

a via-hole electrode is provided to fill the via hole, an upper end surface of the via-hole electrode is connected to a lower surface of the pixel electrode, and a lower end surface of the via-hole electrode is connected to the drain,

the via hole is a step-shaped hole, and an area of the upper end surface of the via-hole electrode is larger than that of the lower end surface of the via-hole electrode,

the via hole includes a large via portion and a small via portion, the via-hole electrode includes a large electrode portion corresponding to the large via portion and a small electrode portion corresponding to the small via portion, and

one end surface of the large electrode portion is connected to the pixel electrode, one end surface of the small electrode portion is connected to the drain, and a height of the large electrode portion along a vertical direction is the same as that of the small electrode portion.

15. The array substrate according to claim 14, wherein

the thin film transistor further includes an organic insulation layer provided above the source and the drain of the thin film transistor, and the via hole penetrates the organic insulation layer.

16. The array substrate according to claim 15, wherein

the thin film transistor further includes an inorganic insulation layer provided between the organic insulation layer and the source and drain of the thin film transistor, and the via hole penetrates the inorganic insulation layer.

17. The array substrate according to claim 16, wherein

the large electrode portion and one part of the small electrode portion are provided in the organic insulation layer, and the other part of the small electrode portion is provided in the inorganic insulation layer.

18. The array substrate according to claim 16, wherein

the organic insulation layer is made of a photosensitive resin, and an etching selectivity ratio between the inorganic insulation layer and the organic insulation layer is no less than 10.