Semiconductor device and method for manufacturing the same

• US 9,508,862 B2
• Filed: 05/21/2015
• Issued: 11/29/2016
• Est. Priority Date: 05/05/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kimura, Hajime
• Primary Examiner(s): Potter, Roy
• Assistant Examiner(s): PATTON, PAUL E
• Application Number:
  US14/718,333
• Publication Number:
  US 20150280009A1
• Time in Patent Office: 558 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.

Claims

1. A semiconductor device comprising:

a transistor over a substrate, the transistor including a gate electrode, a first conductive layer, a second conductive layer, and an oxide semiconductor layer, wherein the gate electrode overlaps with the oxide semiconductor layer;

a third conductive layer over the substrate;

a first insulating layer over the oxide semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer;

a second insulating layer over the first insulating layer, the second insulating layer including an opening;

a pixel electrode over the first insulating layer and the second insulating layer, the pixel electrode electrically connected to one of the first conductive layer and the second conductive layer; and

a color filter between the first insulating layer and the pixel electrode,

wherein the pixel electrode includes a first region and a second region,

wherein the first region is overlapping with the opening,

wherein the pixel electrode is in contact with a top surface of the first insulating layer in the first region, and

wherein the pixel electrode is in contact with a top surface of the second insulating layer in the second region,

wherein the pixel electrode in the first region overlaps with the third conductive layer with the first insulating layer interposed between the pixel electrode and the third conductive layer.

2. The semiconductor device according to claim 1, further comprising:

a fourth conductive layer over the first insulating layer, the fourth conductive layer overlapping with the oxide semiconductor layer.

3. A semiconductor device according to claim 1, further comprising:

a third insulating layer between the oxide semiconductor layer and each of the first conductive layer and the second conductive layer.

4. The semiconductor device according to claim 1, further comprising:

a third insulating layer over the gate electrode,

wherein the oxide semiconductor layer is positioned over the third insulating layer.

5. The semiconductor device according to claim 1, wherein a material of the third conductive layer is the same with a material of the gate electrode.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises at least one of indium, gallium, and zinc.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes a crystal with c-axis alignment.

8. A semiconductor device comprising:

a transistor over a substrate, the transistor including a first gate electrode, a second gate electrode, a first conductive layer, a second conductive layer, and an oxide semiconductor layer, wherein the first gate electrode and the second gate electrode each overlap with the oxide semiconductor layer;

a third conductive layer over the substrate;

a first insulating layer over the oxide semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer;

a second insulating layer over the first insulating layer, the second insulating layer including an opening;

a pixel electrode over the first insulating layer and the second insulating layer, wherein the pixel electrode is electrically connected to one of the first conductive layer and the second conductive layer, and wherein the pixel electrode is electrically connected to one of the first gate electrode and the second gate electrode; and

a color filter between the first insulating layer and the pixel electrode,

wherein the second gate electrode is positioned over the oxide semiconductor layer,

wherein the pixel electrode includes a first region and a second region,

wherein the first region is overlapping with the opening,

wherein the pixel electrode is in contact with a top surface of the first insulating layer in the first region,

wherein the pixel electrode is in contact with a top surface of the second insulating layer in the second region, and

wherein the pixel electrode in the first region overlaps with the third conductive layer with the first insulating layer interposed between the pixel electrode and the third conductive layer.

9. The semiconductor device according to claim 8, wherein the pixel electrode is electrically connected to the second gate electrode.

10. A semiconductor device according to claim 8, further comprising:

a third insulating layer between the oxide semiconductor layer and each of the first conductive layer and the second conductive layer.

11. The semiconductor device according to claim 8, further comprising:

a third insulating layer over the first gate electrode,

wherein the oxide semiconductor layer is positioned over the third insulating layer.

12. The semiconductor device according to claim 8, wherein a material of the third conductive layer is the same with a material of the first gate electrode.

13. The semiconductor device according to claim 8, wherein the oxide semiconductor layer comprises at least one of indium, gallium, and zinc.

14. The semiconductor device according to claim 8, wherein the oxide semiconductor layer includes a crystal with c-axis alignment.