3D semiconductor device

• US 9,509,313 B2
• Filed: 03/06/2011
• Issued: 11/29/2016
• Est. Priority Date: 04/14/2009
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Wurman, Zeev
• Primary Examiner(s): Crawford, Jason M
• Assistant Examiner(s): Bahr, Kurtis R
• Application Number:
  US13/041,406
• Publication Number:
  US 20120193621A1
• Time in Patent Office: 2,095 Days
• Field of Search: 257/E21.506, 257/E25.013, 257/E25.017, 257/685, 257/686, 257/690, 257/691, 257/698, 257723-725, 257/777, 326 37- 41, 326/47
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters

Abstract

A semiconductor device comprising first layer comprising multiplicity of first transistors and, second layer comprising multiplicity of second transistors and, at least one function constructed by the first transistors are structure so it could be replaced by a function constructed by the second transistors.

Claims

1. A semiconductor device comprising:

a first layer comprising a multiplicity of first transistors implementing a plurality of first combinatorial logic functions;

a second layer above or below the first layer comprising a multiplicity of second transistors implementing a plurality of second combinatorial logic functions;

each of said first combinatorial logic functions constructed by said first transistors is replaceable by at least one of said second combinatorial logic functions constructed by said second transistors; and

a plurality of connection paths between said first layer and said second layer,

wherein each of said connection paths comprise a through layer via,

wherein said through layer via has a radius of less than 200 nm, and

wherein said through layer via is through one of said first layer or said second layer.

2. The semiconductor device according to claim 1,

wherein said first layer comprises a plurality of flip-flops each having an input, and

wherein said input is selectively coupleable to at least one of said second transistors.

3. The semiconductor device according to claim 1, further comprising:

a plurality of circuits each performing a comparison between a signal generated by the first transistors and a signal generated by the second transistors.

4. The semiconductor device according to claim 1,

wherein said first layer comprises a plurality of flip-flops each having an output, and

wherein said output is selectively coupleable to at least one of said second combinatorial logic functions.

5. The semiconductor device according to claim 1, further comprising:

an interconnect layer disposed between said first layer and said second layer,

wherein said interconnect layer comprises copper or aluminum, and

wherein either said second transistors are lithographically aligned to said first transistors, or said first transistors are lithographically aligned to said second transistors.

6. A semiconductor device comprising:

a first layer comprising a multiplicity of first transistors implementing a plurality of first combinatorial logic functions;

a second layer above or below the first layer comprising a multiplicity of second transistors implementing a plurality of second combinatorial logic functions; and

each of said first combinatorial logic functions constructed by said first transistors is replaceable by at least one of said second combinatorial logic functions constructed by said second transistors,

wherein said first layer comprises a plurality of flip-flops each having an input, and

wherein said input is selectively coupleable to at least one of said second transistors.

7. The semiconductor device according to claim 6, further comprising:

a plurality of connection paths between said first layer and said second layer,

wherein each of said connection paths comprise a through layer via,

wherein said through layer via has a radius of less than 200 nm, and

wherein said through layer via is through one of said first layer or said second layer.

8. The semiconductor device according to claim 6, further comprising:

an interconnect layer disposed between said first layer and said second layer

wherein said interconnect layer comprises copper or aluminum, and

wherein either said second transistors are lithographically aligned to said first transistors, or said first transistors are lithographically aligned to said second transistors.

9. A semiconductor device comprising:

a first layer comprising a multiplicity of first transistors implementing a plurality of first combinatorial logic functions;

a second layer above or below the first layer comprising a multiplicity of second transistors implementing a plurality of second combinatorial logic functions; and

each of said first combinatorial logic functions constructed by said first transistors is replaceable by at least one of said second combinatorial logic functions constructed by said second transistors,

wherein said first layer comprises a plurality of flip-flops each having an output,

wherein said output is selectively coupleable to at least one of said second combinatorial logic functions.

10. The semiconductor device according to claim 9, further comprising:

a plurality of connection paths between said first layer and said second layer,

wherein each of said connection paths comprise a through layer via,

wherein said through layer via has a radius of less than 200 nm, and

wherein said through layer via is through one of said first layer or said second layer.

11. The semiconductor device according to claim 9, further comprising:

an interconnect layer disposed between said first layer and said second layer

wherein said interconnect layer comprises copper or aluminum, and

wherein either said second transistors are lithographically aligned to said first transistors, or said first transistors are lithographically aligned to said second transistors.

12. A semiconductor device comprising:

a first layer comprising a multiplicity of first transistors; and

a second layer comprising a multiplicity of second transistors,

wherein operation of said device is adapted to be repaired if non-functional by replacing a combinatorial logic or analog function constructed by said first transistors with a combinatorial logic or analog function constructed by said second transistors; and

a plurality of connection paths between said first layer and said second layer,

wherein each of said connection paths comprise a through layer via,

wherein said through layer via has a radius of less than 200 nm, and

wherein said through layer via is through one of said first layer or said second layer.

13. The semiconductor device according to claim 12, further comprising:

an interconnect layer disposed between said first layer and said second layer

wherein said interconnect layer comprises copper or aluminum, and

wherein either said second transistors are lithographically aligned to said first transistors, or said first transistors are lithographically aligned to said second transistors.

14. A semiconductor device comprising:

a first layer comprising a multiplicity of first transistors; and

a second layer comprising a multiplicity of second transistors,

wherein operation of said device is adapted to be repaired if non-functional by replacing a combinatorial logic or analog function constructed by said first transistors with a combinatorial logic or analog function constructed by said second transistors; and

an interconnect layer disposed between said first layer and said second layer

wherein said interconnect layer comprises copper or aluminum, and

wherein either said second transistors are lithographically aligned to said first transistors, or said first transistors are lithographically aligned to said second transistors.

15. The semiconductor device according to claim 14, further comprising:

a plurality of connection paths between said first layer and said second layer,

wherein each of said connection paths comprise a through layer via,

wherein said through layer via has a radius of less than 200 nm, and

wherein said through layer via is through one of said first layer or said second layer.

16. A semiconductor device comprising:

a first layer comprising a multiplicity of first transistors;

a second layer comprising a multiplicity of second transistors,

wherein operation of said device is adapted to be repaired if non-functional by replacing a combinatorial logic function constructed by said first transistors with a combinatorial logic function constructed by said second transistors; and

a plurality of connection paths between said first layer and said second layer,

wherein each of said connection paths comprise a through layer via,

wherein said through layer via has a radius of less than 200 nm, and

wherein said through layer via is through one of said first layer or said second layer.

17. The semiconductor device according to claim 16,

wherein said first layer comprises a plurality of flip-flops each having an input, and

wherein said input is selectively coupleable to at least one of said second transistors.

18. The semiconductor device according to claim 16, further comprising:

a plurality of circuits each performing a comparison between a signal generated by the first transistors and a signal generated by the second transistors.

19. The semiconductor device according to claim 16,

wherein said first layer comprises a plurality of flip-flops each having an output, and

wherein said output is selectively coupleable to at least one of said combinatorial logic function constructed by said second transistors.

20. The semiconductor device according to claim 16, further comprising:

an interconnect layer disposed between said first layer and said second layer,

wherein said interconnect layer comprises copper or aluminum, and

wherein either said second transistors are lithographically aligned to said first transistors, or said first transistors are lithographically aligned to said second transistors.