Synchronous transfer of streaming data in a distributed antenna system

• US 9,509,487 B2
• Filed: 06/15/2015
• Issued: 11/29/2016
• Est. Priority Date: 03/31/2010
• Status: Active Grant

• Current Assignee: Outdoor Wireless Networks LLC (CommScope Holding Company, Inc.)
• Original Assignee: CommScope Technologies, LLC (CommScope Holding Company, Inc.)
• Inventors: McAllister, Donald Robert, Ranson, Christopher Goodman, Phillips, Fred William
• Primary Examiner(s): Torres, Juan A
• Application Number:
  US14/739,465
• Publication Number:
  US 20150280900A1
• Time in Patent Office: 533 Days
• Field of Search: 375/371, 375/376, 375/329
• US Class Current: 1/1
• CPC Class Codes: H04J 3/0658 Clock or time synchronisation among packet nodes
• CPC Class Codes: H04L 1/0625 Transmitter arrangements
• CPC Class Codes: H04L 1/0631 Receiver arrangements
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04W 88/085 Access point devices with remote components

Abstract

Method and apparatus for generating a jitter reduced clock signal from signal transmitted over a communication medium includes receiving, with high speed data interface circuitry, a modulated signal that includes a binary encoded data stream. A recovered clock signal is generated from the modulated signal and tracks the long-term drift in the modulated signal. A jitter reduced clock signal is generated by filtering the recovered clock signal with a filtering circuit having a bandwidth sufficient to remove jitter while allowing the jitter reduced clock signal to track the drift in the modulated signal.

Claims

1. A method of generating a jitter reduced clock signal from signal transmitted over a communication medium, the method comprising:

receiving, with high speed data interface circuitry, a modulated signal that includes a binary encoded data stream;

generating a recovered clock signal from the modulated signal that tracks the long-term drift in the modulated signal; and

generating a jitter reduced clock signal by filtering the recovered clock signal with a filtering circuit having a bandwidth sufficient to remove jitter while allowing the jitter reduced clock signal to track the drift in the modulated signal.

2. The method of claim 1 further comprising generating a jitter reduced clock signal by filtering the recovered clock signal using at least one of a phase-locked loop, a frequency-locked loop or a narrowband filter.

3. The method of claim 1 further comprising scaling the frequency of the jitter reduced clock signal to produce at least one scaled clock signal.

4. The method of claim 1, wherein the high speed data interface circuitry includes at least a one gigabit per second (Gbps) Ethernet interface.

5. The method of claim 1, wherein the communication medium is a communication cable having at least one twisted pair cable.

6. The method of claim 4, wherein the Ethernet interface is synchronous or asynchronous.

7. A distributed antenna system, comprising:

a master unit that clocks a binary encoded data stream onto high speed data interface circuitry using a modulated signal; and

at least one remote unit that receives the modulated signal and binary encoded data stream from the master unit, the at least one remote unit including;

a clock recovery circuit that is configured to generate a recovered clock signal from the modulated signal that tracks long-term drift in the modulated signal; and

a filtering circuit to filter the recovered clock signal, the filtering circuit having a bandwidth sufficient to remove jitter while allowing the jitter reduced clock signal to track the drift in the modulated signal for generating a jitter reduced clock signal.

8. The system of claim 7 wherein the filtering circuit includes at least one of a phase-locked loop, a frequency-locked loop or a narrowband filter.

9. The system of claim 7 further comprising a scaling circuit configured to scale the frequency of the stable recovered clock signal to generate an output signal at a predetermined target frequency.

10. The system of claim 7 wherein the high speed data interface circuitry is coupled to a communication medium, between the master unit and at least one remote unit, having at least one twisted pair cable.

11. The system of claim 7, the master unit further including:

RF transceiver circuitry for communicating with a base transceiver station;

an auxiliary interface for communicating at least one of control data, maintenance data, Ethernet data, or WiFi data; and

a processor that multiplexes data from the RF transceiver circuitry and the auxiliary interface for transmission to the at least one remote unit via the master unit high speed data interface circuitry, and that de-multiplexes data received from the master unit high speed data interface circuitry for transmission to the base transceiver station via the RF transceiver circuitry.

12. The system of claim 7, wherein the high speed data interface circuitry is an at least a one gigabit per second (Gbps) Ethernet interface.

13. A remote unit for use in a distributed antenna system, the remote unit configured for coupling with a master unit to transceive a modulated signal with the master unit, the remote unit comprising:

a clock recovery circuit that is configured to generate a recovered clock signal from the modulated signal that tracks long-term drift in the modulated signal; and

a filtering circuit to filter the recovered clock signal, the filtering circuit having a bandwidth sufficient to remove jitter while allowing the jitter reduced clock signal to track the drift in the modulated signal for generating a jitter reduced clock signal.

14. The remote unit of claim 13 wherein the filtering circuit includes at least one of a phase-locked loop, a frequency-locked loop or a narrowband filter.

15. The remote unit of claim 13 further comprising a scaling circuit configured to scale the frequency of the stable recovered clock signal to generate an output signal at a predetermined target frequency.

16. The remote unit of claim 13 further comprising:

high speed data interface circuitry for transceiving the modulated signal with the master unit;

RF transceiver circuitry for communicating cellular and non-cellular data with a subscriber unit;

an auxiliary interface for communicating at least one of control data, maintenance data, Ethernet data, or WiFi data; and

a processing unit that de-multiplexes data from the high speed data interface circuitry for transmission by the RF transceiver circuitry or the auxiliary interface, and that multiplexes data from the RF transceiver circuitry and the auxiliary interface for transmission on the high speed data interface circuitry.

17. The remote unit of claim 16 wherein the processing unit is configured to adjust the rate of data being transmitted on the high speed data interface circuitry to match the capability of that interface circuitry by excluding low priority data from the multiplexed stream.

18. The remote unit of claim 16, wherein the data that is multiplexed to the remote unit high speed data interface circuitry includes at least one of digitized RF cellular voice data, digitized RF non-cellular voice data, digitized RF cellular data, digitized RF non-cellular data, control data, maintenance data, Ethernet data or WiFi data.

19. The remote unit of claim 16, wherein the high speed data interface circuitry includes at least a one gigabit per second (Gbps) Ethernet interface.