Video processing circuit and related method for merging video output streams with data stream for transmission

• US 9,509,921 B2
• Filed: 07/24/2015
• Issued: 11/29/2016
• Est. Priority Date: 11/24/2008
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Shih, Yang-Hung, Lin, Hung-Der, Po, Tang-Hung, Chiu, Sau-Kwo
• Primary Examiner(s): WONG, ALLEN C
• Application Number:
  US14/807,900
• Publication Number:
  US 20150334312A1
• Time in Patent Office: 494 Days
• Field of Search: 375/240.26
• US Class Current: 1/1
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2370/14 Use of low voltage differential signaling [LVDS] for display data communication
• CPC Class Codes: G09G 5/003 Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto specific for a CRT G09G1/165; for a flat panel G09G3/2092
• CPC Class Codes: G09G 5/377 for mixing or overlaying two or more graphic patterns G09G5/02, G09G5/397 take precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 21/431 Generation of visual interfaces for content selection or interaction; Content or additional data rendering
• CPC Class Codes: H04N 21/434 Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/44016 involving splicing one content stream with another content stream, e.g. for substituting a video clip
• CPC Class Codes: H04N 5/265 Mixing
• CPC Class Codes: H04N 7/0806 the signals being two or more video signals H04N7/0803, H04N7/081 take precedence

Abstract

A video processing circuit includes a video generating unit for generating a video output stream, a data generating unit (e.g. graphic generating unit) for providing a data stream (e.g. graphical stream), and a communication interface circuit. The communication interface circuit has a mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through a channel. In the mode, the communication interface circuit merges the video output stream and the data stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the data stream, and compressing the video output stream. The communication interface circuit may have another mode provided for mixing the video output stream and the data stream to transmit a mixed video output stream through the channel.

Claims

1. A video processing circuit, comprising:

a video generating unit for generating a video output stream according to a video input stream;

a data generating unit for providing a data stream; and

a communication interface circuit, coupled to the video generating unit and the data generating unit, the communication interface circuit having a mode provided for merging the video output stream and the data stream to transmit a first merged signal through a channel, wherein in the mode, a first part of bandwidth of the channel is utilized for transmitting the video output stream and a second part of bandwidth of the channel is utilized for transmitting the data stream;

wherein in the mode, the communication interface circuit merges the video output stream and the data stream by compressing the video output stream.

2. The video processing circuit of claim 1, further comprising:

a post-processing device, coupled to the communication interface circuit, for receiving the first merged signal through the channel in the mode.

3. The video processing circuit of claim 1, wherein the communication interface circuit compresses the video output stream by:

transferring the video output stream from a first color depth format to a second color depth format;

replacing actual color values of the video output stream with color indexes of the video output stream;

or

transferring the video output stream into a packet format.

4. The video processing circuit of claim 1, wherein the communication interface circuit is a low voltage differential signal (LVDS) interface circuit.

5. The video processing circuit of claim 1, wherein data stream comprises an on-screen display (OSD) data and the data generating unit is an on-screen display (OSD) encoder.

6. The video processing circuit of claim 1, further comprising:

a first signal receiver, coupled to the communication interface circuit, for receiving the first merged signal and extracting the video output stream and the data stream from the first merged signal;

a video post-processing unit, coupled to the first signal receiver, for receiving and post-processing the video output stream extracted from the first merged signal to generate a processed video output stream;

a decoding unit, coupled to the first signal receiver, for decoding the data stream to generate a decoded data stream;

a mixer, coupled to the video post-processing unit and the decoding unit, for mixing the processed video output stream with the decoded data stream to generate a second merged signal; and

a second signal transmitter, coupled to the mixer, for outputting the second merged signal.

7. The video processing circuit of claim 1, wherein the communication interface circuit has another mode provided for mixing the video output stream and the data stream to transmit a mixed video output stream through the channel, wherein in the other mode, bandwidth of the channel is used for transmitting the mixed video output stream.

8. A video processing circuit, comprising:

a video generating unit for generating a video output stream according to a video input stream;

a data generating unit for providing a data stream; and

a communication interface circuit, coupled to the video generating unit and the data generating unit, the communication interface circuit having a mode provided for merging the video output stream and the data stream to transmit a first merged signal through a channel, wherein in the mode, a first part of bandwidth of the channel is utilized for transmitting the video output stream and a second part of bandwidth of the channel is utilized for transmitting the data stream;

wherein in the mode, the communication interface circuit merges the video output stream and the data stream by increasing a working frequency of the communication interface circuit to increase a bandwidth of the channel.

9. The video processing circuit of claim 8, further comprising:

a post-processing device, coupled to the communication interface circuit, for receiving the first merged signal through the channel in the mode.

10. The video processing circuit of claim 8, wherein the communication interface circuit is a low voltage differential signal (LVDS) interface circuit.

11. The video processing circuit of claim 8, further comprising:

a first signal receiver, coupled to the communication interface circuit, for receiving the first merged signal and extracting the video output stream and the data stream from the first merged signal;

a video post-processing unit, coupled to the first signal receiver, for receiving and post-processing the video output stream extracted from the first merged signal to generate a processed video output stream;

a decoding unit, coupled to the first signal receiver, for decoding the data stream to generate a decoded data stream;

a mixer, coupled to the video post-processing unit and the decoding unit, for mixing the processed video output stream with the decoded data stream to generate a second merged signal; and

a second signal transmitter, coupled to the mixer, for outputting the second merged signal.

12. The video processing circuit of claim 8, wherein the communication interface circuit has another mode provided for mixing the video output stream and the data stream to transmit a mixed video output stream through the channel, wherein in the other mode, bandwidth of the channel is used for transmitting the mixed video output stream.

13. A video processing circuit, comprising:

a video generating unit for generating a video output stream according to a video input stream;

a data generating unit for providing a data stream; and

a communication interface circuit, coupled to the video generating unit and the data generating unit, the communication interface circuit having a mode provided for merging the video output stream and the data stream to transmit a first merged signal through a channel, wherein in the mode, a first part of bandwidth of the channel is utilized for transmitting the video output stream and a second part of bandwidth of the channel is utilized for transmitting the data stream;

wherein in the mode, the communication interface circuit merges the video output stream and the data stream by using positions for transmitting a portion of video control signals in the video output stream to transmit the data stream.

14. The video processing circuit of claim 13, further comprising:

a post-processing device, coupled to the communication interface circuit, for receiving the first merged signal through the channel in the mode.

15. The video processing circuit of claim 13, wherein the communication interface circuit is a low voltage differential signal (LVDS) interface circuit.

16. The video processing circuit of claim 13, wherein data stream comprises an on-screen display (OSD) data and the data generating unit is an on-screen display (OSD) encoder.

17. The video processing circuit of claim 13, further comprising:

a first signal receiver, coupled to the communication interface circuit, for receiving the first merged signal and extracting the video output stream and the data stream from the first merged signal;

a video post-processing unit, coupled to the first signal receiver, for receiving and post-processing the video output stream extracted from the first merged signal to generate a processed video output stream;

a decoding unit, coupled to the first signal receiver, for decoding the data stream to generate a decoded data stream;

a mixer, coupled to the video post-processing unit and the decoding unit, for mixing the processed video output stream with the decoded data stream to generate a second merged signal; and

a second signal transmitter, coupled to the mixer, for outputting the second merged signal.

18. The video processing circuit of claim 17, further comprising:

a video output device, coupled to the second signal transmitter, for receiving the second merged signal and displaying video images according to the second merged signal.

19. The video processing circuit of claim 13, wherein the communication interface circuit has another mode provided for mixing the video output stream and the data stream to transmit a mixed video output stream through the channel, wherein in the other mode, bandwidth of the channel is used for transmitting the mixed video output stream.

20. A method for merging video output streams with a data stream for transmission, the method comprising:

generating a video output stream according to a video input stream;

providing a data stream; and

providing a mode for merging the video output stream and the data stream to transmit a first merged signal to a post-processing chip through a channel, wherein in the mode, a first part of bandwidth of the channel is utilized for transmitting the video output stream and a second part of bandwidth of the channel is utilized for transmitting the data stream;

wherein in the mode, the step of merging the video output stream and the data stream comprises using positions for transmitting a portion of video control signals in the video output stream to transmit the data stream.

21. The method of claim 20, wherein in the mode, the step of merging the video output stream and the data stream comprises:

using positions for transmitting a portion of video control signals in the video output stream to transmit the data stream.

22. The method of claim 20, further comprising:

receiving the first merged signal and extracting the video output stream and the data stream from the first merged signal;

receiving and post-processing the video output stream extracted from the first merged signal to generate a processed video output stream;

decoding the data stream to generate a decoded data stream;

mixing the processed video output stream with the decoded data stream to generate a second merged signal; and

outputting the second merged signal.

23. The method of claim 20, further comprising:

providing another mode for mixing the video output stream and the data stream to transmit a mixed video output stream through the channel, wherein in the other mode, bandwidth of the channel is used for transmitting the mixed video output stream.