Systems, methods, and devices for energy and power metering

• US 9,513,319 B1
• Filed: 09/25/2015
• Issued: 12/06/2016
• Est. Priority Date: 11/25/2014
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Fosler, Ross Martin, Keeser, Christopher Corson
• Primary Examiner(s): Assouad, Patrick
• Assistant Examiner(s): CURTIS, SEAN M
• Application Number:
  US14/866,225
• Publication Number:
  US 20160334445A1
• Time in Patent Office: 438 Days
• Field of Search: 324/761.01, 324/764.01, 324/771, 361/157, 361/659, 361/661, 455/115.4, 455/226.4
• US Class Current: 1/1
• CPC Class Codes: G01R 15/142 Arrangements for simultaneous measurements of several parameters employing techniques covered by groups G01R15/14 - G01R15/26
• CPC Class Codes: G01R 15/20 using galvano-magnetic devices, e.g. Hall-effect devices , i.e. measuring a magnetic field via the interaction between a current and a magnetic field, e.g. magneto resistive or Hall effect devices
• CPC Class Codes: G01R 21/133 by using digital technique
• CPC Class Codes: G01R 22/10 using digital techniques
• CPC Class Codes: G05B 19/056 Programming the PLC
• CPC Class Codes: G05B 2219/15097 Power supply
• CPC Class Codes: G05F 1/66 Regulating electric power

Abstract

Disclosed herein are systems, methods, and devices for power and energy metering. Devices may include first processing logic coupled to an isolator and configured to receive a first bit stream from a first modulator via the isolator. The first bit stream may be generated by the first modulator based on a first analog signal. The first processing logic may be further configured to receive a second bit stream from a second modulator via the isolator. The second bit stream may be generated by the second modulator based on a second analog signal. The processing logic may be further configured to generate a third bit stream based on a combination of the first bit stream with the second bit stream. The devices may also include second processing logic configured to generate an output signal based on one or more values of the third bit stream. The output signal may characterize a measurement of electrical power associated with an electrical circuit.

Claims

1. A device comprising:

first processing logic coupled to an isolator and configured to receive a first bit stream from a first modulator via the isolator, the first bit stream being generated by the first modulator based on a first analog signal, the first processing logic further configured to receive a second bit stream from a second modulator via the isolator, the second bit stream being generated by the second modulator based on a second analog signal, the first processing logic further configured to generate a third bit stream based on a combination of the first bit stream with the second bit stream after the first bit stream and second bit stream have passed through the isolator; and

second processing logic configured to generate an output signal based, at least in part, on one or more values of the third bit stream, the output signal characterizing a measurement of an electrical power associated with an electrical circuit, wherein the second processing logic comprises a digital filter configured to filter the third bit stream based on at least one property of a power supply.

2. The device of claim 1, wherein the first modulator is a first sigma delta modulator, and wherein the second modulator is a second sigma delta modulator.

3. The device of claim 1, wherein the first analog signal is a voltage signal, and wherein the second analog signal is a current signal.

4. The device of claim 1, wherein the first processing logic is configured to combine the first bit stream with the second bit stream in accordance with a logical AND operation.

5. The device of claim 1, wherein the second processing logic comprises computational logic configured to average values included in the third bit stream, and wherein the second processing logic is further configured to generate the output signal based on an average of values included in the third bit stream.

6. The device of claim 1, wherein the second processing logic is configured to integrate values included in the third bit stream, and further configured to generate the output signal based on an integration of values included in the third bit stream.

7. The device of claim 1 further comprising an isolator positioned between the first processing logic and the first and second modulators.

8. The device of claim 1, wherein the output signal further characterizes a measured electrical energy associated with the first analog signal and the second analog signal.

9. The device of claim 1, wherein the second processing logic is configured to provide the output signal to a power controller.

10. A method comprising:

receiving a first analog signal at a first modulator;

receiving a second analog signal at a second modulator;

generating, using the first modulator, a first bit stream based on the first analog signal;

generating, using the second modulator, a second bit stream based on the second analog signal;

generating, using first processing logic, a third bit stream based on a combination of the first bit stream with the second bit stream after the first bit stream and second bit stream have passed through an isolator; and

generating, using second processing logic, an output signal based on, at least in part, one or more values of the third bit stream, the output signal characterizing an electrical power associated with an electrical circuit,

wherein the generating of the output signal comprises filtering, using a digital filter, the third bit stream based on at least one property of a power supply.

11. The method of claim 10, wherein the first analog signal is a voltage signal, and wherein the second analog signal is a current signal.

12. The method of claim 10, wherein the generating of the third bit stream comprises;

implementing a logical AND operation on the first bit stream and the second bit stream.

13. The method of claim 10, wherein the generating of the output signal comprises averaging values included in the third bit stream.

14. The method of claim 10, wherein the generating of the output signal comprises integrating values included in the third bit stream.

15. A system comprising:

a first portion of a power component, the first portion comprising

a modulator block comprising a first modulator and a second modulator, the first modulator configured to convert a first analog signal into a first bit stream, and the second modulator configured to convert a second analog signal into a second bit stream;

an isolator coupled to the first portion of the power component and configured to receive the first bit stream and the second bit stream from the modulator block;

a second portion of the power component coupled to the isolator, the second portion comprising;

first processing logic coupled to the isolator and configured to receive the first bit stream and the second bit stream from the isolator, the first processing logic configured to generate a third bit stream based on a combination of the first bit stream with the second bit stream after the first bit stream and second bit stream have passed through the isolator;

second processing logic configured to generate an output signal characterizing an electrical power associated with an electrical circuit, the output signal based, at least in part, on one or more values of the third bit stream, wherein the second processing logic comprises a digital filter configured to filter the third bit stream based on at least one property of a power supply; and

a controller configured to receive the output signal from the second processing logic, and further configured to generate a control signal based on the output signal.

16. The system of claim 15, wherein the first modulator is a first sigma delta modulator, wherein the second modulator is a second sigma delta modulator, wherein the first analog signal is a voltage signal, and wherein the second analog signal is a current signal.

17. The system of claim 15, wherein the power component is a power inverter included in a solar panel, and wherein the first processing logic is configured to combine the first bit stream with the second bit stream in accordance with a logical AND operation.

18. The system of claim 15, wherein the second processing logic is configured to integrate values included in the third bit stream, and further configured to generate the output signal based on a result of the integration of the values in the third bit stream.