System and method for power management

• US 9,513,662 B2
• Filed: 01/04/2013
• Issued: 12/06/2016
• Est. Priority Date: 01/04/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chin, Jennifer, Lim, Su Wei, Teoh, Poh Thiam, Song, Ting Lok, E, Sun Zheng, Gan, Say Cheong, Lim, Sujea, Lim, Ming Yi
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Yen, Paul J
• Application Number:
  US13/734,612
• Publication Number:
  US 20140195830A1
• Time in Patent Office: 1,432 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/1626 with a single-body enclosure integrating a flat display, e.g. Personal Digital Assistants [PDAs]
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3218 of display devices
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.

Claims

1. A system, comprising:

a processor;

a plurality of Peripheral Component Interconnect Express (PCIe) ports; and

a memory to store instructions that, when executed by the processor, perform operations comprising

evaluating the plurality of PCIe ports;

in response to determining that a clock request (CLKREQ) pin associated with at least one of the plurality of the PCIe ports is not receiving a signal, disabling a squelch function associated with the system; and

in response to determining that the CLKREQ pin is not receiving the signal, gating power associated with a physical layer (PHY) of the system for an unpopulated port of the plurality of PCIe ports.

2. The system of claim 1, wherein the clock request pin is used to detect a hot plug event to power up the PHY.

3. The system of claim 1, wherein the system is a mobile computing device configured to be docked at a docking station.

4. The system of claim 1, wherein a docking interconnect is included in the system.

5. The system of claim 1, wherein the plurality of PCIe ports are unpopulated and configured to perform the disabling the squelch function.

6. The system of claim 1, wherein a root port of the plurality of PCIe ports provides power to the PHY in response to the system being docked.

7. The system of claim 1, wherein a root port of the plurality of PCIe ports provides power to the PHY in response to the system being connected to an external monitor.

8. The system of claim 1, wherein the operations further comprise:

enabling the squelch function, in response to determining that the CLKREQ pin is receiving a signal.

9. An apparatus to manage power for at least one processor, the apparatus comprising:

a plurality of Peripheral Component Interconnect Express (PCIe) ports; and

logic, the logic at least partially including hardware logic, to

evaluate the plurality of PCIe ports;

in response to determining that a clock request (CLKREQ) pin associated with at least one of the plurality of the PCIe ports is not receiving a signal, disable a squelch function associated with the apparatus; and

in response to determining that the CLKREQ pin is not receiving the signal, gate power associated with a physical layer (PHY) of the apparatus for an unpopulated port of the plurality of PCIe ports.

10. The apparatus of claim 9, wherein the clock request pin is used to detect a hot plug event to power up the PHY.

11. The apparatus of claim 9, wherein the apparatus is a mobile computing device configured to be docked at a docking station.

12. The apparatus of claim 9, wherein a docking interconnect is included in the apparatus.

13. The apparatus of claim 9, wherein the logic enables the squelch function, in response to determining that the CLKREQ pin is receiving a signal.

14. A method implemented by an electronic device, the method comprising:

evaluating a plurality of Peripheral Component Interconnect Express (PCIe) ports included in the electronic device;

in response to determining that a clock request (CLKREQ) pin associated with at least one of the plurality of the PCIe ports is not receiving a signal, disabling a squelch function associated with the electronic device; and

in response to determining that the CLKREQ in is not receiving the signal, gating power associated with a physical layer (PHY) of the electronic device for an unpopulated port of the plurality of PCIe ports.

15. The method of claim 14, wherein the clock request pin is used to detect a hot plug event to power up the PHY.

16. The method of claim 14, wherein the electronic device is a mobile computing device configured to be docked at a docking station.

17. The method of claim 14, wherein a docking interconnect is included in the electronic device.

18. The method of claim 14, further comprising:

enabling the squelch function, in response to determining that the CLKREQ pin is receiving a signal.