Core synchronization mechanism in a multi-die multi-core microprocessor
First Claim
1. A microprocessor, comprising:
- a plurality of semiconductor dies;
a bus, coupling the plurality of semiconductor dies;
a plurality of processing cores, wherein a distinct subset of the plurality of processing cores is located on each of the plurality of semiconductor dies;
wherein each die of the plurality of semiconductor dies comprises;
a control unit, configured to selectively control a respective clock signal to each core of the subset of cores of the die; and
wherein, for each core of the subset of cores of the die, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other of the plurality of dies;
wherein collectively all of the control units are configured to simultaneously turn on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores;
wherein each die of the plurality of semiconductor dies comprises;
a respective control register associated with each of the plurality of processing cores of the microprocessor such that each of the control registers of the die has a corresponding control register of the other of the plurality of dies; and
wherein, for each core of the subset of cores of the die, in response to the core writing the value to the core'"'"'s respective control register, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the corresponding control register on the other of the plurality of dies;
wherein to collectively simultaneously turn on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores, each of the control units is configured to turn on the clock signals to the subset of cores of its die after the value has been written to all of the control registers of its die; and
wherein each control unit is configured to delay updating the control register of its die with the value written by the respective core such that the value is simultaneously written to the corresponding control register on the other of the plurality of dies.
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Abstract
A microprocessor includes a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, and a plurality of processing cores. A distinct subset of the processing cores is located on each of the semiconductor dies. Each die comprises a control unit configured to selectively control a respective clock signal to each of the subset of cores of the die. For each core of the subset, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other die. Collectively all of the control units are configured to simultaneously turn on the clock signals to all of the processing cores after the clock signals have been turned off to all of the processing cores.
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Citations
16 Claims
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1. A microprocessor, comprising:
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a plurality of semiconductor dies; a bus, coupling the plurality of semiconductor dies; a plurality of processing cores, wherein a distinct subset of the plurality of processing cores is located on each of the plurality of semiconductor dies; wherein each die of the plurality of semiconductor dies comprises; a control unit, configured to selectively control a respective clock signal to each core of the subset of cores of the die; and wherein, for each core of the subset of cores of the die, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other of the plurality of dies; wherein collectively all of the control units are configured to simultaneously turn on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores; wherein each die of the plurality of semiconductor dies comprises; a respective control register associated with each of the plurality of processing cores of the microprocessor such that each of the control registers of the die has a corresponding control register of the other of the plurality of dies; and wherein, for each core of the subset of cores of the die, in response to the core writing the value to the core'"'"'s respective control register, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the corresponding control register on the other of the plurality of dies; wherein to collectively simultaneously turn on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores, each of the control units is configured to turn on the clock signals to the subset of cores of its die after the value has been written to all of the control registers of its die; and wherein each control unit is configured to delay updating the control register of its die with the value written by the respective core such that the value is simultaneously written to the corresponding control register on the other of the plurality of dies. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for synchronizing cores in a microprocessor having a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, a plurality of processing cores wherein a distinct subset of the plurality of processing cores is located on each of the plurality of semiconductor dies, and wherein each die of the plurality of semiconductor dies comprises a control unit configured to selectively control a respective clock signal to each core of the subset of cores of the die, the method comprising:
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for each core of the subset of cores of the die; writing, by the core, a value to the control unit; turning off, by the control unit, the respective clock signal to the core; and writing, by the control unit, the value over the bus to the control unit of the other of the plurality of dies; simultaneously turning on, by collectively all of the control units, the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores; wherein each die of the plurality of semiconductor dies includes a respective control register associated with each of the plurality of processing cores of the microprocessor such that each of the control registers of the die has a corresponding control register of the other of the plurality of dies; for each core of the subset of cores of the die, in response to the core writing the value to the core'"'"'s respective control register, turning off, by the control unit, the respective clock signal to the core and writing the value over the bus to the corresponding control register on the other of the plurality of dies; wherein said collectively simultaneously turning on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores comprises turning on, by each of the control units, the clock signals to the subset of cores of its die after the value has been written to all of the control registers of its die; and wherein each control unit is configured to delay updating the control register of its die with the value written by the respective core such that the value is simultaneously written to the corresponding control register on the other of the plurality of dies. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:
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computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising; first program code for specifying a plurality of semiconductor dies; second program code for specifying a bus, coupling the plurality of semiconductor dies; third program code for specifying a plurality of processing cores, wherein a distinct subset of the plurality of processing cores is located on each of the plurality of semiconductor dies; fourth program code for specifying, for each die of the plurality of semiconductor dies, a control unit, configured to selectively control a respective clock signal to each core of the subset of cores of the die, wherein, for each core of the subset of cores of the die, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other of the plurality of dies; wherein collectively all of the control units are configured to simultaneously turn on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores; wherein each die of the plurality of semiconductor dies comprises; a respective control register associated with each of the plurality of processing cores of the microprocessor such that each of the control registers of the die has a corresponding control register of the other of the plurality of dies; and wherein, for each core of the subset of cores of the die, in response to the core writing the value to the core'"'"'s respective control register, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the corresponding control register on the other of the plurality of dies; wherein to collectively simultaneously turn on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores, each of the control units is configured to turn on the clock signals to the subset of cores of its die after the value has been written to all of the control registers of its die; and wherein each control unit is configured to delay updating the control register of its die with the value written by the respective core such that the value is simultaneously written to the corresponding control register on the other of the plurality of dies. - View Dependent Claims (16)
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Specification