Core synchronization mechanism in a multi-die multi-core microprocessor

• US 9,513,687 B2
• Filed: 05/19/2014
• Issued: 12/06/2016
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Parks, Terry
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Stewart, Kevin
• Application Number:
  US14/281,488
• Publication Number:
  US 20150067368A1
• Time in Patent Office: 932 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A microprocessor includes a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, and a plurality of processing cores. A distinct subset of the processing cores is located on each of the semiconductor dies. Each die comprises a control unit configured to selectively control a respective clock signal to each of the subset of cores of the die. For each core of the subset, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other die. Collectively all of the control units are configured to simultaneously turn on the clock signals to all of the processing cores after the clock signals have been turned off to all of the processing cores.

Claims

1. A microprocessor, comprising:

a plurality of semiconductor dies;

a bus, coupling the plurality of semiconductor dies;

a plurality of processing cores, wherein a distinct subset of the plurality of processing cores is located on each of the plurality of semiconductor dies;

wherein each die of the plurality of semiconductor dies comprises;

a control unit, configured to selectively control a respective clock signal to each core of the subset of cores of the die; and

wherein, for each core of the subset of cores of the die, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other of the plurality of dies;

wherein collectively all of the control units are configured to simultaneously turn on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores;

wherein each die of the plurality of semiconductor dies comprises;

a respective control register associated with each of the plurality of processing cores of the microprocessor such that each of the control registers of the die has a corresponding control register of the other of the plurality of dies; and

wherein, for each core of the subset of cores of the die, in response to the core writing the value to the core'"'"'s respective control register, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the corresponding control register on the other of the plurality of dies;

wherein to collectively simultaneously turn on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores, each of the control units is configured to turn on the clock signals to the subset of cores of its die after the value has been written to all of the control registers of its die; and

wherein each control unit is configured to delay updating the control register of its die with the value written by the respective core such that the value is simultaneously written to the corresponding control register on the other of the plurality of dies.

2. The microprocessor of claim 1,

wherein each die of the plurality of semiconductor dies comprises a respective indicator associated with each core of the plurality of processing cores of the microprocessor that indicates whether the core is enabled or disabled;

and

wherein to collectively simultaneously turn on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores, each of the control units is configured to turn on the clock signals to the subset of cores of its die after the clock signals have been turned off to all of the plurality of processing cores whose respective indicator indicates the associated core is enabled.

3. The microprocessor of claim 2, wherein each of the plurality of processing cores is configured to initiate an update of its respective associated indicator.

4. The microprocessor of claim 3, the control units are configured to collectively simultaneously update all of the indicators associated with a core of the plurality of processing cores in response to the core initiating an update of its respective associated indicator.

5. The microprocessor of claim 1, wherein the value written by the core to the control unit includes a selective wakeup indicator, wherein collectively all of the control units are configured to turn on the respective clock signal to only a temporally last of the plurality of processing cores to write the value.

6. The microprocessor of claim 1, wherein each die of the plurality of semiconductor dies comprises a status register, from which is readable by each of the subset of cores of the die, after collectively all of the control units have simultaneously turned on the clock signals to all of the plurality of processing cores, a lowest common value of a sleep state portion of the value written by each of the plurality of processing cores.

7. The microprocessor of claim 1, further comprising:

wherein each of the control units is configured to determine that the value written by each of the plurality of processing cores specifies a group of the plurality of processing cores that is less than all of the plurality of processing cores; and

wherein collectively all of the control units are configured to simultaneously turn on the clock signals to the group of the plurality of processing cores after the clock signals have been turned off to the group of the plurality of processing cores without regard for whether the plurality of processing cores excluded from the group have written the value.

8. A method for synchronizing cores in a microprocessor having a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, a plurality of processing cores wherein a distinct subset of the plurality of processing cores is located on each of the plurality of semiconductor dies, and wherein each die of the plurality of semiconductor dies comprises a control unit configured to selectively control a respective clock signal to each core of the subset of cores of the die, the method comprising:

for each core of the subset of cores of the die;

writing, by the core, a value to the control unit;

turning off, by the control unit, the respective clock signal to the core; and

writing, by the control unit, the value over the bus to the control unit of the other of the plurality of dies;

simultaneously turning on, by collectively all of the control units, the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores;

wherein each die of the plurality of semiconductor dies includes a respective control register associated with each of the plurality of processing cores of the microprocessor such that each of the control registers of the die has a corresponding control register of the other of the plurality of dies;

for each core of the subset of cores of the die, in response to the core writing the value to the core'"'"'s respective control register, turning off, by the control unit, the respective clock signal to the core and writing the value over the bus to the corresponding control register on the other of the plurality of dies;

wherein said collectively simultaneously turning on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores comprises turning on, by each of the control units, the clock signals to the subset of cores of its die after the value has been written to all of the control registers of its die; and

wherein each control unit is configured to delay updating the control register of its die with the value written by the respective core such that the value is simultaneously written to the corresponding control register on the other of the plurality of dies.

9. The method of claim 8, wherein each die of the plurality of semiconductor dies includes a respective indicator associated with each core of the plurality of processing cores of the microprocessor that indicates whether the core is enabled or disabled, wherein said collectively simultaneously turning on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores comprises turning on, by each of the control units, the clock signals to the subset of cores of its die after the clock signals have been turned off to all of the plurality of processing cores whose respective indicator indicates the associated core is enabled.

10. The method of claim 9, further comprising:

initiating, by one of the plurality of processing cores, an update of its respective associated indicator.

11. The method of claim 10, further comprising:

collectively simultaneously updating, by the control units, all of the indicators associated with a core of the plurality of processing cores in response to said initiating by the core an update of its respective associated indicator.

12. The method of claim 8, wherein the value written by the core to the control unit includes a selective wakeup indicator, wherein collectively all of the control units turn on the respective clock signal to only a temporally last of the plurality of processing cores to write the value.

13. The method of claim 8, wherein each die of the plurality of semiconductor dies includes a status register, the method further comprising:

reading, by each of the subset of cores of the die, after collectively all of the control units have simultaneously turned on the clock signals to all of the plurality of processing cores, a lowest common value of a sleep state portion of the value written by each of the plurality of processing cores.

14. The method of claim 8, further comprising:

determining, by each of the control units, that the value written by each of the plurality of processing cores specifies a group of the plurality of processing cores that is less than all of the plurality of processing cores; and

simultaneously turning on, collectively by all of the control units, the clock signals to the group of the plurality of processing cores after the clock signals have been turned off to the group of the plurality of processing cores without regard for whether the plurality of processing cores excluded from the group have written the value.

15. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising;

first program code for specifying a plurality of semiconductor dies;

second program code for specifying a bus, coupling the plurality of semiconductor dies;

third program code for specifying a plurality of processing cores, wherein a distinct subset of the plurality of processing cores is located on each of the plurality of semiconductor dies;

fourth program code for specifying, for each die of the plurality of semiconductor dies, a control unit, configured to selectively control a respective clock signal to each core of the subset of cores of the die, wherein, for each core of the subset of cores of the die, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other of the plurality of dies;

wherein collectively all of the control units are configured to simultaneously turn on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores;

wherein each die of the plurality of semiconductor dies comprises;

a respective control register associated with each of the plurality of processing cores of the microprocessor such that each of the control registers of the die has a corresponding control register of the other of the plurality of dies; and

wherein, for each core of the subset of cores of the die, in response to the core writing the value to the core'"'"'s respective control register, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the corresponding control register on the other of the plurality of dies;

wherein to collectively simultaneously turn on the clock signals to all of the plurality of processing cores after the clock signals have been turned off to all of the plurality of processing cores, each of the control units is configured to turn on the clock signals to the subset of cores of its die after the value has been written to all of the control registers of its die; and

wherein each control unit is configured to delay updating the control register of its die with the value written by the respective core such that the value is simultaneously written to the corresponding control register on the other of the plurality of dies.

16. The computer program product of claim 15, wherein the at least one non-transitory computer usable medium is selected from the set of a disk, tape, or other magnetic, optical, or electronic storage medium.