Measurement of performance scalability in a microprocessor

• US 9,513,688 B2
• Filed: 03/16/2013
• Issued: 12/06/2016
• Est. Priority Date: 03/16/2013
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Varma, Ankush, Sistla, Krishnakanth V., Shrall, Jeremy J., Ananthakrishnan, Avinash N.
• Primary Examiner(s): Rehman, Mohammed
• Assistant Examiner(s): Sampath, Gayathri
• Application Number:
  US13/844,815
• Publication Number:
  US 20140281612A1
• Time in Patent Office: 1,361 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A scalability algorithm causes a processor to initialize a performance indicator counter, operate at an initial frequency of the first clock signal for a first duration, and determine, based on the performance indicator counter, an initial performance of the first processing core. The algorithm may then cause the processor to operate at a second frequency of the first clock signal for a second duration and determine, based on the performance indicator counter, a second performance of the first processing core. A performance scalability of the first processing core may be determined based on the initial performance and the second performance and an operational parameter, such as one or more clock frequencies and/or supply voltage(s), may be changed based on the determined scalability.

Claims

1. A processor comprising:

a first processing core;

a second processing core; and

a power control unit to provide a first clock signal to the first processing core and a second clock signal to the second processing core, the power control unit to;

initialize a performance indicator counter;

cause the first processing core to operate at an initial frequency of the first clock signal for a first duration;

after the first duration, determine, based on the performance indicator counter, a first performance value of a first performance parameter of the first processing core;

cause the first processing core to operate at a second frequency of the first clock signal for a second duration, the second duration substantially shorter than the first duration;

after the second duration, determine, based on the performance indicator counter, a second performance value of the first performance parameter of the first processing core;

calculate a performance scalability of the first performance parameter of the first processing core based on the first performance value and the second performance value;

modify at least one of the first clock signal and the second clock signal based on the performance scalability, including to cause the first processing core to operate at the second frequency of the first clock signal for the second duration and to return to operate at the initial frequency of the first clock signal if the performance scalability is less than a first threshold value, wherein the first threshold value is based on an acceptable performance cost.

2. The processor of claim 1, wherein the power control unit is to cause at least one of the first processing core and the second processing core to:

operate at a third frequency of the first clock signal, wherein the third frequency is based on the performance scalability.

3. The processor of claim 1, wherein the performance indicator counter is to indicate instructions retired by the first processing core.

4. The processor of claim 3, wherein the performance indicator counter is to indicate instructions of a first type retired.

5. The processor of claim 1, wherein the power control unit is to:

determine a performance scalability of the second processing core;

identify a more scalable of the first processing core and the second processing core; and

modify a frequency of the more scalable processing core.

6. The processor of claim 5, wherein the power control unit is to:

determine, from a power measurement reading, a power scalability of the first processing core and the second processing core; and

increase a frequency of a more power scalable processing core.

7. A method, comprising:

providing a first clock signal to a first processing core and a second clock signal to a second processing core;

initializing a performance indicator counter;

causing the first processing core to operate at an initial frequency of the first clock signal for a first duration;

after the first duration, determining, based on the performance indicator counter, a first performance value of a first performance parameter of the first processing core;

causing the first processing core to operate at a second frequency of the first clock signal for a second duration, the second duration substantially shorter than the first duration;

after the second duration, determining, based on the performance indicator counter, a second performance value of the first performance parameter of the first processing core;

calculating a performance scalability of the first performance parameter of the first processing core based on the first performance value and the second performance value; and

causing the first processing core to return to operate at the initial frequency of the first clock signal after the second duration if the performance scalability is less than a first threshold value, wherein the first threshold value is based on an acceptable performance cost.

8. The method of claim 7, further comprising:

operating at a third frequency of the first clock signal, wherein the third frequency is based on the performance scalability.

9. The method of claim 7, wherein the performance indicator counter indicates instructions retired by the first processing core.

10. The method of claim 9, wherein the performance indicator counter indicates instructions of a first type retired.

11. The method of claim 7, further comprising:

determining a performance scalability of the second processing core;

identifying a more scalable of the first processing core and the second processing core; and

modifying a frequency of the more scalable processing core.

12. The method of claim 11, further comprising:

determining, from a power measurement reading, a power scalability of the first processing core and the second processing core; and

increasing a frequency of a more power scalable processing core.

13. A non-transitory computer readable storage medium including processor-executable instructions to cause a processor to perform operations comprising:

providing a first clock signal to a first processing core and a second clock signal to a second processing core initializing a performance indicator counter;

causing the first processing core to operate at an initial frequency of the first clock signal for a first duration;

after the first duration, determining, based on the performance indicator counter, a first performance value of a first performance parameter of the first processing core;

causing the first processing core to operate at a second frequency of the first clock signal for a second duration, the second duration substantially shorter than the first duration;

after the second duration, determining, based on the performance indicator counter, a second performance value of the first performance parameter of the first processing core;

calculating a performance scalability of the first performance parameter of the first processing core based on the first performance value and the second performance value; and

causing the first processing core to return to operate at the initial frequency of

the first clock signal after the second duration if the performance scalability is less than a first threshold value, wherein the first threshold value is based on an acceptable performance cost.

14. The non-transitory computer readable storage medium of claim 13, further comprising instructions to cause the processor to perform operations comprising:

operating at a third frequency of the first clock signal, wherein the third frequency is based on the performance scalability.

15. The non-transitory computer readable storage medium of claim 13, wherein the performance indicator counter indicates instructions retired by the first processing core.

16. The non-transitory computer readable storage medium of claim 15, wherein the performance indicator counter indicates instructions of a first type retired.

17. The non-transitory computer readable storage medium of claim 13, further comprising instructions to cause the processor to perform operations comprising:

determining a performance scalability of the second processing core;

identifying a more scalable of the first processing core and the second processing core; and

modifying a frequency of the more scalable processing core.

18. The non-transitory computer readable storage medium of claim 17, further comprising instructions to cause the processor to perform operations comprising:

determining, from a power measurement reading, a power scalability of the first processing core and the second processing core; and

increasing a frequency of a more power scalable processing core.