Methods of managing power in network computer systems

• US 9,513,695 B2
• Filed: 07/26/2013
• Issued: 12/06/2016
• Est. Priority Date: 06/24/2008
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Virident Systems Inc. (Western Digital Corporation)
• Inventors: Karamcheti, Vijay, Okin, Kenneth A., Ganapathy, Kumar
• Primary Examiner(s): NGUYEN, HIEP T
• Application Number:
  US13/952,567
• Publication Number:
  US 20150032940A1
• Time in Patent Office: 1,229 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0674 Disk device
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.

Claims

1. A method comprising:

sharing, with a network computer system, a plurality of disk-read-only-memory (disk-ROM) devices amongst two or more processor complexes, wherein each processor complex includes a plurality processors;

powering down at least one processor complex in response to a reduced computing load; and

maintaining data stored in the plurality of disk-ROM devices for other processor complexes that remain powered up.

2. The method of claim 1, further comprising:

prior to powering down the at least one processor complex, transferring main memory data in a main memory of the at least one processor complex into one or more of the plurality of disk-ROM devices, including one or more electrically erasable programmable read-only memory (EEPROM) devices.

3. The method of claim 2, further comprising:

powering up the at least one processor complex in response to an increased computing load; and

transferring saved main memory data back into the main memory of the at least one processor complex from the one or more of the plurality of disk-ROM devices in response to powering up the at least one processor complex.

4. The method of claim 1, further comprising:

powering up the at least one processor complex in response to an increased computing load.

5. The method of claim 1, wherein

each of the plurality of disk-ROM devices include a non-volatile memory array to maintain the data stored therein.

6. The method of claim 1, wherein

a total memory space of a shared memory cloud provided by the plurality of disk-ROMs is initially partitioned into a plurality of memory space partitions,

the at least one processor complex is assigned to operate with at least one memory space partition, and

the method further includes

upon powering down of the at least one processor complex, repartitioning the at least one memory space partition into a second one or more memory space partitions.

7. The method of claim 6, wherein

the second one or more memory space partitions are re-assigned for usage by remaining powered-up processor complexes.

8. The method of claim 1, wherein

a total memory space of a shared memory cloud provided by the plurality of disk-ROMs is initially partitioned into a plurality of memory space partitions, and the method further includes

assigning one or more memory space partitions for usage by a plurality of processor complexes.