Method and system for atomically writing scattered information in a solid state storage device

• US 9,513,831 B2
• Filed: 10/23/2015
• Issued: 12/06/2016
• Est. Priority Date: 05/17/2013
• Status: Active Grant

• Current Assignee: Palisade Technologies, LLP
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Walsh, James J., Tomlin, Andrew J.
• Primary Examiner(s): SHIN, CHRISTOPHER B
• Application Number:
  US14/921,418
• Publication Number:
  US 20160048354A1
• Time in Patent Office: 410 Days
• Field of Search: 710/62, 711/104, 711/154
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1471 involving logging of persistent data for recovery
• CPC Class Codes: G06F 11/1474 in transactions G06F16/20 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/06 Digital input from, or digital output to, record carriers , e.g. RAID, emulated record carriers or networked record carriers
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Disclosed herein are several methods and systems for handling atomic write commands that reach scattered address ranges. One embodiment includes a method of performing an operation in a data storage device, the method comprising: receiving an atomic write command; obtaining a plurality of ranges of logical addresses affected by the atomic write command; for each of the plurality of affected ranges, assigning metadata information to track completion of a write operation performed at that range; performing the write operations in the ranges of logical addresses; updating the metadata information upon completion of the write operations in the ranges; and deferring an update to a translation map of the data storage device until the metadata information has been updated.

Claims

1. A method of performing an operation in a data storage device, the method comprising:

receiving a plurality of atomic write commands;

grouping together the plurality of atomic write commands into a single atomic operation;

obtaining a plurality of ranges of logical addresses affected by the plurality of atomic write commands;

for each of the plurality of affected ranges, assigning metadata information to track completion of a write operation performed at that range;

performing the write operations in the ranges of logical addresses;

updating the metadata information upon completion of the write operations in the ranges; and

deferring an update to a translation map of the data storage device until the metadata information has been updated.

2. The method of claim 1, wherein the grouping comprises:

assigning metadata to each of the plurality of atomic write commands indicating that each of the plurality of atomic write commands is part of a grouped atomic operation; and

assigning metadata to each of the plurality of atomic write commands indicating an atomic group identifier.

3. The method of claim 1, wherein each range in the plurality of ranges of logical addresses affected is non-contiguous.

4. The method of claim 1, wherein the metadata for each range is unique to the write operation performed at the associated range of logical addresses.

5. The method of claim 4, wherein the metadata for each write operation associated with the plurality of atomic write commands comprises:

a sequence number of a plurality of sequence numbers assigned to each of the plurality of ranges; and

a slot number configured to store one of the sequence numbers.

6. The method of claim 5, wherein updating the metadata information upon completion of the write operations in the ranges comprises:

changing, in the power-safe storage, the sequence numbers associated with the plurality of atomic write commands after all the write operations are completed.

7. The method of claim 5, wherein a list of all the slot numbers associated with the plurality of ranges and a status of the write operation performed at the associated range of logical addresses are stored in a power-safe storage.

8. The method of claim 6, wherein the changing comprises, when a write operation performed at one of the ranges completes, changing the sequence number associated with that range.

9. The method of claim 8, further comprising:

after all the data specified by the plurality of atomic write commands have been written and the metadata updated, updating the translation map; and

acknowledging a completion of the plurality of atomic write commands to a host coupled to the data storage device after the translation map has been updated.

10. A controller in a data storage device, the controller comprising:

a processor configured to;

receive a plurality of atomic write commands;

group together the plurality of atomic write commands into a single atomic operation;

obtain a plurality of ranges of logical addresses affected by the plurality of atomic write commands;

for each of the plurality of affected ranges, assign metadata information to track completion of a write operation performed at that range;

perform the write operations in the ranges of logical addresses;

update the metadata information upon completion of the write operations in the ranges; and

defer an update to a translation map of the data storage device until the metadata information has been updated.

11. The controller of claim 10, wherein the processor is configured to group together the plurality of atomic write commands by:

assigning metadata to each of the plurality of atomic write commands indicating that each of the plurality of atomic write commands is part of a grouped atomic operation; and

assigning metadata to each of the plurality of atomic write commands indicating an atomic group identifier.

12. The controller of claim 10, wherein each range in the plurality of ranges of logical addresses affected is non-contiguous.

13. The controller of claim 10, wherein the metadata for each range is unique to the write operation performed at the associated range of logical addresses.

14. The controller of claim 13, wherein the metadata for each write operation associated with the plurality of atomic write commands comprises:

a sequence number of a plurality of sequence numbers assigned to each of the plurality of ranges; and

a slot number configured to store one of the sequence numbers.

15. The controller of claim 14, wherein updating the metadata information upon completion of the write operations in the ranges comprises:

changing, in the power-safe storage, the sequence numbers associated with the plurality of atomic write commands after all the write operations are completed.

16. The controller of claim 14, wherein a list of all the slot numbers associated with the plurality of ranges and a status of the write operation performed at the associated range of logical addresses are stored in a power-safe storage.

17. The controller of claim 15, wherein the changing comprises, when a write operation performed at one of the ranges completes, changing the sequence number associated with that range.

18. The controller of claim 10, configured to:

after all the data specified by the plurality of atomic write commands have been written and the metadata updated, update the translation map; and

acknowledge a completion of the plurality of atomic write commands to a host coupled to the data storage device after the translation map has been updated.

19. A data storage device comprising:

a plurality of non-volatile solid-state memory devices; and

a controller comprising;

a processor configured to;

receive a plurality of atomic write commands;

group together the plurality of atomic write commands into a single atomic operation;

obtain a plurality of ranges of logical addresses affected by the plurality of atomic write commands;

for each of the plurality of affected ranges, assign metadata information to track completion of a write operation performed at that range;

perform the write operations in the ranges of logical addresses;

update the metadata information upon completion of the write operations in the ranges; and

defer an update to a translation map of the data storage device until the metadata information has been updated.

20. The data storage device of claim 19, wherein the processor is configured to group together the plurality of atomic write commands by:

assigning metadata to each of the plurality of atomic write commands indicating that each of the plurality of atomic write commands is part of a grouped atomic operation; and

assigning metadata to each of the plurality of atomic write commands indicating an atomic group identifier.