Systems and methods for utilizing wear leveling windows with non-volatile memory systems

• US 9,514,043 B1
• Filed: 05/12/2015
• Issued: 12/06/2016
• Est. Priority Date: 05/12/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Patel, Leena
• Primary Examiner(s): Lane, John A
• Application Number:
  US14/710,135
• Publication Number:
  US 20160335178A1
• Time in Patent Office: 574 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

Systems and methods for utilizing wear leveling windows with non-volatile memory systems are disclosed. In one implementation, a memory management module of a non-volatile memory system compares a metric reflecting wear of a memory block to a wear leveling window and determines whether a wear leveling indicator associated with the memory block restricts performing a wear leveling operation on the memory block. The memory management module performs a wear leveling operation on the memory block in response to determining that the metric reflecting wear of the memory block falls outside the wear leveling window and determining that the wear leveling indicator does not restrict performing a wear leveling operation on the memory block. After performing the wear leveling operation, the memory management module places the memory block on a free block list.

Claims

1. In a memory management module of a non-volatile memory system, the non-volatile memory system comprising a non-volatile memory that comprises a plurality of memory blocks, a method comprising:

comparing a program/erase cycle count associated with a memory block of the non-volatile memory system to a wear leveling window, the wear leveling window comprising a ceiling limit and a floor limit;

determining whether a wear leveling indicator associated with the memory block restricts performing a wear leveling operation on the memory block;

performing a wear leveling operation on the memory block in response to determining that the program/erase cycle count associated with the memory block is within a defined range of one of the ceiling limit or the floor limit of the wear leveling window and determining that the wear leveling indicator associated with the memory block does not restrict performing a wear leveling operation on the memory block; and

placing the memory block on a free block list after the wear leveling operation is performed on the memory block.

2. The method of claim 1, wherein at least one of the ceiling limit or the floor limit of the wear leveling window comprises a range of program/erase count values.

3. The method of claim 1, further comprising:

adjusting at least one of the ceiling limit or the floor limit of the wear leveling window; and

setting the wear leveling indicator associated with the memory block to not restrict performing a wear leveling operation on the memory block.

4. The method of claim 3, wherein adjusting at least one of the ceiling limit or the floor limit of the wear leveling window comprises decreasing a distance between the ceiling limit and the floor limit.

5. The method of claim 3, wherein at least one of the ceiling limit or the floor limit of the wear leveling window are adjusted based on a determination of at least one of:

a rate at which the program/erase count associated with the memory block approaches at least one of the ceiling limit or the floor limit of the wear leveling window;

a distance between the ceiling limit and the floor limit of the wear leveling window in relation to a spread of program/erase counts associated with memory blocks at the non-volatile memory system;

a number of wear leveling operations since the memory management module last adjusted the wear leveling window;

a number of memory blocks on the free block list;

or

a life stage of the non-volatile memory system.

6. The method of claim 1, wherein the wear leveling indicator comprises a flag.

7. The method of claim 1, wherein the wear leveling indicator comprises a counter.

8. The method of claim 1, wherein the wear leveling indicator is stored in at least one of a header file of the memory block or a look-up table stored at the non-volatile memory system.

9. The method of claim 1, wherein the memory block comprises a silicon substrate and a plurality of memory cells forming at least two memory layers vertically disposed with respect to each other to form a monolithic three-dimensional structure, wherein at least one layer is vertically disposed with respect to the silicon substrate.

10. A non-volatile memory system comprising:

a non-volatile memory comprising a plurality of memory units; and

processing circuitry in communication with the non-volatile memory, the processing circuitry comprising;

a memory management module configured to compare a program/erase cycle count associated with a memory unit to a ceiling limit and a floor limit;

to perform a wear leveling operation on the memory unit based on the comparison of the program/erase cycle count associated with the memory unit and the ceiling limit and the floor limit;

to place the memory unit on a free memory unit list after performing the wear leveling operation on the memory unit; and

to adjust at least one of the ceiling limit or the floor limit.

11. The non-volatile memory system of claim 10, where the memory unit is a memory block.

12. The non-volatile memory system of claim 10, wherein at least one of the ceiling limit or the floor limit comprises a range of program/erase cycle counts.

13. The non-volatile memory system of claim 10, wherein the memory management module is configured to adjust the at least one of the ceiling limit or the floor limit based on a determination of at least one of:

a rate at which the program/erase count associated with the memory unit approaches at least one of the ceiling limit or the floor limit;

a distance between the ceiling limit and the floor limit in relation to a spread of program/erase counts associated with memory units of the plurality of memory units;

a number of wear leveling operations since the memory management module last adjusted at least one of the ceiling limit or the floor limit;

a number of memory units on the free memory unit list;

or

a life stage of the non-volatile memory system.

14. The non-volatile memory system of claim 10, wherein the memory management module is further configured to store information in a header of the memory unit to restrict the memory management system from performing a wear leveling operation on the memory unit.

15. The non-volatile memory system of claim 14, wherein the information stored in the header of the memory unit comprises a counter.

16. In a memory management module of a non-volatile memory system, the non-volatile memory system comprising a non-volatile memory that comprises a plurality of memory units, a method comprising:

determining that a metric reflecting wear of a memory unit falls outside of a wear leveling window;

performing a wear leveling operation on the memory unit; and

adjusting a wear leveling indicator associated with the memory unit to restrict the memory management module from performing a future wear leveling operation on the memory unit.

17. The method of claim 16, wherein the wear leveling indictor is stored in a header file of the memory unit.

18. The method of claim 16, wherein the wear leveling indicator is stored in a look-up table stored at the non-volatile memory system.

19. The method of claim 16, wherein the wear leveling indictor comprises a flag and adjusting the wear leveling indicator comprises setting a state of the flag of the wear leveling indicator.

20. The method of claim 16, wherein the wear leveling indictor comprises a counter and adjusting the wear leveling indicator comprises setting a value of the counter of the wear leveling indicator to its maximum value.

21. The method of claim 16, wherein the metric reflecting wear of the memory block comprises a program/erase cycle count of the memory unit.

22. The method of claim 16, wherein the metric reflecting wear of the memory unit comprises an age of the memory unit.

23. The method of claim 16, wherein the metric reflecting wear of the memory unit comprises an indicator of a relative wear of the memory unit in relation to another memory unit.