Magnetic storage cell memory with back hop-prevention

• US 9,514,796 B1
• Filed: 06/26/2015
• Issued: 12/06/2016
• Est. Priority Date: 06/26/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Panagopoulos, Georgios, Augustine, Charles, Tomishima, Shigeki, Wu, Wei, Lu, Shih-Lien, Tschanz, James W., Naeimi, Helia
• Primary Examiner(s): Phan, Trong
• Application Number:
  US14/751,801
• Publication Number:
  US 20160379700A1
• Time in Patent Office: 529 Days
• Field of Search: 365/148, 365/158, 365/163, 365/171, 365/173, 365/175
• US Class Current: 1/1
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits

Abstract

An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

Claims

1. An apparatus, comprising:

a semiconductor chip memory array having resistive storage cells;

a comparator to compare a first word to be written into the array against a second word stored in the array at a location targeted by a write operation that will write the first word into the array; and

,

circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with an increasing write current intensity with each successive iteration.

2. The apparatus of claim 1 further comprising a circuit to increase a write current amplitude with each successive iteration.

3. The apparatus of claim 2 further comprising write circuitry having a plurality of transistors to drive a bit line, where, with each successive iteration, a number of the transistors that is activated is increased.

4. The apparatus of claim 1 further comprising a circuit to increase an amount of time that a write current is applied with each successive iteration.

5. The apparatus of claim 3 wherein said circuit includes a counter to count clock cycles.

6. The apparatus of claim 1 further comprising a first circuit to increase a write current amplitude and a second circuit to increase an amount of time that a write current is applied where one or both of the write current amplitude and the amount of time that a write current is applied is increased with each successive iteration.

7. The apparatus of claim 6 wherein both the write current amplitude and the amount of time that the write current is applied is increased with each successive iteration.

8. An apparatus, comprising:

a semiconductor chip memory array having resistive storage cells;

a comparator to compare a first word to be written into the array against a second word stored in the array at a location targeted by a write operation that will write the first word into the array; and

,

circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration, where, an applied write current intensity for each successive iteration is based on a percentage of storage cells that is expected to be set by the applied write current intensity.

9. The apparatus of claim 8 further comprising a circuit to increase a write current amplitude with each successive iteration.

10. The apparatus of claim 9 further comprising write circuitry having a plurality of transistors to drive a bit line, where, with each successive iteration, a number of the transistors that is activated is increased.

11. The apparatus of claim 8 further comprising a circuit to increase an amount of time that a write current is applied with each successive iteration.

12. The apparatus of claim 11 wherein said circuit includes a counter to count clock cycles.

13. The apparatus of claim 8 further comprising a first circuit to increase a write current amplitude and a second circuit to increase an amount of time that a write current is applied where one or both of the write current amplitude and the amount of time that write current is applied is increased with each successive iteration.

14. The apparatus of claim 13 wherein both the write current amplitude and the amount of time that the write current is applied is increased with each successive iteration.

15. A computing system, comprising:

a plurality of processing cores; and

,

a semiconductor chip memory having;

i) a memory array having resistive storage cells;

ii) a comparator to compare a first word to be written into the array against a second word stored in the array at a location targeted by a write operation that will write the first word into the array; and

,

iii) circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with an increasing write current intensity with each successive iteration.

16. The computing system of claim 15 further comprising a circuit to increase a write current amplitude with each successive iteration.

17. The computing system of claim 15 further comprising a circuit to increase an amount of time that a write current is applied with each successive iteration.

18. The computing system of claim 15 further comprising a first circuit to increase a write current amplitude and a second circuit to increase an amount of time that a write current is applied where one or both of the write current amplitude and an amount of time that the write current is applied is increased with each successive iteration.

19. The apparatus of claim 18 wherein both the write current amplitude and the amount of time that the write current is applied is increased with each successive iteration.

20. The apparatus of claim 15 wherein the resistive storage cells are magnetic storage cells.