Semiconductor memory having electrically floating body transistor

• US 9,514,803 B2
• Filed: 12/01/2015
• Issued: 12/06/2016
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US14/956,253
• Publication Number:
  US 20160078921A1
• Time in Patent Office: 371 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4067 for memory cells of the bipolar type
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

Claims

1. A semiconductor memory cell comprising:

a transistor comprising a source region, a floating body region, a drain region, and a gate;

a first bipolar device having a first floating base region, a first emitter, and a first collector; and

a second bipolar device having a second floating base region, a second emitter, and a second collector,

wherein said first floating base region and said second floating base region are common to said floating body region;

wherein said first collector is common to said second collector;

wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell, and

wherein said transistor is usable to access said memory cell.

2. The semiconductor memory cell of claim 1, wherein said state of said memory cell is stored in at least one of said first floating base region, said second floating base region or said floating body region.

3. The semiconductor memory cell of claim 1, wherein said state of said memory cell is maintained through a back bias applied to said first and second collectors.

4. The semiconductor memory cell of claim 3, wherein said back-bias applied to said first and second collectors is a constant voltage bias.

5. The semiconductor memory cell of claim 3, wherein said back-bias applied to said first and second collectors is a periodic pulse of voltage.

6. The semiconductor memory cell of claim 3, wherein said back bias results in at least two stable states.

7. The semiconductor memory cell of claim 1, wherein said transistor is formed in a fin structure.

8. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;

a transistor comprising a source region, a floating body region, a drain region, and a gate;

a first bipolar device having a first floating base region, a first emitter, and a first collector; and

a second bipolar device having a second floating base region, a second emitter, and a second collector;

wherein said first floating base region and said second floating base region are common to said floating body region;

wherein said first collector is common to said second collector; and

wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell, wherein said transistor is usable to access said memory cell; and

wherein said first and second collectors are commonly connected to at least two of said memory cells.

9. The semiconductor memory array of claim 8, wherein said state of said memory cell is stored in at least one of said first floating base region, said second floating base region, or said floating body region.

10. The semiconductor memory array of claim 8, wherein a back bias applied to said first and second collectors maintains the state of said memory cells connected to said first and second collectors.

11. The semiconductor memory array of claim 10, wherein said back-bias applied to said first and second collectors is a constant voltage bias.

12. The semiconductor memory array of claim 10, wherein said back-bias applied to said first and second collectors is a periodic pulse of voltage.

13. The semiconductor memory array of claim 10, wherein said back bias results in at least two stable states.

14. The semiconductor memory array of claim 8, wherein said transistor is formed in a fin structure.

15. An integrated circuit comprising:

an array of semiconductor memory cells formed in a semiconductor substrate having at least one surface, the array comprising;

said semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;

a transistor comprising a source region, a floating body region, a drain region, and a gate;

a first bipolar device having a first floating base region, a first emitter, and a first collector; and

a second bipolar device having a second floating base region, a second emitter, and a second collector;

a first control circuit configured to provide electrical signals to said first and second collectors, and

a second control circuit configured to provide electrical signals to said transistor to access said memory cell;

wherein said first floating base region and said second floating base region are common to said floating body region;

wherein said first collector is common to said second collector;

wherein at least one of said first bipolar device and said second bipolar device maintains a state of said memory cell;

wherein said transistor is usable to access said memory cell;

wherein said first and second collectors are commonly connected to at least two of said memory cell.

16. The integrated circuit of claim 15, wherein said first control circuit provides electrical signals to said first and second collectors to maintain the state of said memory cells connected to said first and second collectors.

17. The integrated circuit of claim 16, wherein said electrical signals to said first and second collectors are constant voltage biases.

18. The integrated circuit of claim 16, wherein said electrical signals to said first and second collectors are periodic pulses of voltage.

19. The integrated of claim 16, wherein said electrical signals to said first and second collectors result in at least two stable states.

20. The integrated circuit of claim 15, wherein said second control circuit provides electrical signals to said transistors to read the states of said memory cells.