EEPROM architecture wherein each bit is formed by two serially connected cells

• US 9,514,820 B2
• Filed: 11/19/2014
• Issued: 12/06/2016
• Est. Priority Date: 11/19/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Tailliet, Francois
• Primary Examiner(s): Graham, Kretelia
• Application Number:
  US14/547,199
• Publication Number:
  US 20160141032A1
• Time in Patent Office: 748 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

An integrated circuit memory includes memory cells arranged in an array with rows and columns, each column including a first bit line and a second bit line. Each memory cell is formed by: a first select transistor with a first source-drain path; a second select transistor with a second source-drain path; a first floating gate transistor with a third source-drain path; and a second floating gate transistor with a fourth source-drain path. The first, second, third and fourth source-drain paths are coupled in series between the first bit line and the second bit line. The word line for each row of the memory is coupled to the gate terminals of the first and second select transistors. The control gate line for each row in coupled to the gate terminals of the first and second floating gate transistors.

Claims

1. An integrated circuit, comprising:

a first bit line;

a second bit line; and

a first memory cell configured to store a single data bit, comprising;

a first select transistor;

a second select transistor;

a first floating gate transistor having a first source node and configured for storing said single data bit; and

a second floating gate transistor having a second source node and configured for storing said single data bit;

wherein source-drain paths of the first and second select transistors and the first and second floating gate transistors are coupled in series with each other between the first bit line and the second bit line, wherein said first and second source nodes are directly connected to each other but not connected to any other circuit;

wherein gate terminals of the first and second select transistors are connected to a same first word line for the first memory cell.

2. The integrated circuit of claim 1, wherein gate terminals of the first and second floating gate transistors are connected to a same control gate line for the first memory cell.

3. The integrated circuit of claim 2, further comprising a control circuit coupled to the word line, the control gate line, the first bit line and the second bit line, said control circuit configured to perform read, erase and program operations on the first memory cell.

4. The integrated circuit of claim 1, further comprising:

a second memory cell, comprising;

a third select transistor;

a fourth select transistor;

a third floating gate transistor having a third source node; and

a fourth floating gate transistor having a fourth source node;

wherein source-drain paths of the third and fourth select transistors and the third and fourth floating gate transistors are coupled in series with each other between the first bit line and the second bit line, with said third and fourth source nodes are directly connected to each other but not connected to any other circuit.

5. The integrated circuit of claim 4,

wherein gate terminals of the first and second select transistors are connected to said same first word line for the first memory cell;

wherein gate terminals of the third and fourth select transistors are connected to a same second word line for the second memory cell;

wherein gate terminals of the first and second floating gate transistors are connected to a first control gate line for the first memory cell; and

wherein gate terminals of the third and fourth floating gate transistors are connected to a second control gate line for the second memory cell.

6. The integrated circuit of claim 1, further comprising:

a third bit line;

a fourth bit line; and

a second memory cell, comprising;

a third select transistor;

a fourth select transistor;

a third floating gate transistor having a third source node; and

a fourth floating gate transistor having a fourth source node;

wherein source-drain paths of the third and fourth select transistors and the third and fourth floating gate transistors are coupled in series with each other between the third bit line and the fourth bit line, with said third and fourth source nodes are directly connected to each other but not connected to any other circuit.

7. The integrated circuit of claim 6,

wherein gate terminals of the first, second, third and fourth select transistors are connected to said same first word line;

and

wherein gate terminals of the first, second, third and fourth floating gate transistors are connected to a same control gate line for the first and second memory cells.

8. The integrated circuit of claim 1, further comprising:

a substrate;

a diffusion region formed in the substrate to support the series coupled source-drain paths of the first and second select transistors and first and second floating gate transistors;

a plurality of polysilicon regions formed on top of the substrate to form gate terminals of the first and second select transistors and first and second floating gate transistors.

9. The integrated circuit of claim 8, wherein the polysilicon regions extend perpendicular to the diffusion region.

10. The integrated circuit of claim 8, further comprising:

a first metal contact with the diffusion region at a first end of the series coupled source-drain paths; and

a second metal contact with the diffusion region at a second end of the series coupled source-drain paths.

11. The integrated circuit of claim 10, further comprising a metallization level over the substrate including a first metallization line in electrical contact with the first metal contact and defining the first bit line.

12. The integrated circuit of claim 11, further comprising an additional metallization level including a second metallization line in electrical contact with the second metal contact and defining the second bit line.

13. The integrated circuit of claim 12, wherein the first and second metallization lines extend parallel to the diffusion region.

14. The integrated circuit of claim 12, wherein the second metallization line extends over, without contacting, the first metal contact.

15. The integrated circuit of claim 12, wherein the second metallization line extends over the first metallization line.

16. The integrated circuit of claim 11, wherein the first metallization line passes around, without contacting, the second metal contact.

17. The integrated circuit of claim 1, further comprising a control circuit coupled to the first bit line and second bit line, said control circuit configured to couple the first bit line to a reference voltage and couple the second bit line to a sense amplifier during a read operation on the first memory cell.

18. The integrated circuit of claim 1, wherein gate terminals of the first and second floating gate transistors are connected to first and second control gate lines, respectively, for the first memory cell.

19. The integrated circuit of claim 18, further comprising a control circuit coupled to the word line, the first and second control gate lines, the first bit line and the second bit line, said control circuit configured to perform read, erase, program and test operations on the first memory cell.

20. The integrated circuit of claim 19, wherein during the test operation the control circuit applies a different control voltage to the first and second control gate lines and separately senses a charge retention state of each of the first and second floating gate transistors.

21. An integrated circuit, comprising:

a non-volatile memory including a plurality of memory cells arranged in an array with rows and columns;

wherein each column includes a first bit line and a second bit line; and

wherein each memory cell comprises;

a first select transistor with a first source-drain path;

a first floating gate transistor with a second source-drain path series connected to the first source-drain path at a first node;

a second floating gate transistor with a third source-drain path series connected to the second source-drain path at a second node; and

a second select transistor with a fourth source-drain path series connected to the third source-drain path at a third node;

wherein the first, second, third and fourth source-drain paths are coupled in series between the first bit line and the second bit line;

wherein each row includes a word line;

wherein the word line for each row is coupled to the gate terminals of the first and second select transistors of each memory cell in that row; and

wherein there is no source control signal applied to said second node from external to said memory cell during any mode of operation of said memory cell.

22. The integrated circuit of claim 21, wherein each row includes a control gate line, and wherein the control gate line is coupled to gate terminals of the first and second floating gate transistors of each memory cell in that row.

23. The integrated circuit of claim 21, further comprising a control circuit coupled to the word lines, the control gate lines, the first bit lines and the second bit lines, said control circuit configured to perform read, erase and program operations on the plurality of memory cells.

24. The integrated circuit of claim 23, further comprising a sense amplifier circuit, wherein said control circuit is configured, when performing the read operation on said each memory cell, to couple the first bit line to a reference voltage and couple the second bit line to the sense amplifier circuit.

25. The integrated circuit of claim 21, further comprising:

a substrate;

a diffusion region formed in the substrate to support each of the series coupled first, second, third and fourth source-drain paths;

a plurality of polysilicon regions formed on top of the substrate to form gate terminals of the first and second select transistors and the first and second floating gate transistors.

26. The integrated circuit of claim 25, further comprising:

a first metal contact with the diffusion region at a first end of the series coupled source-drain paths;

a second metal contact with the diffusion region at a second end of the series coupled source-drain paths;

a metallization level over the substrate including a first metallization line in electrical contact with the first metal contact and defining the first bit line for one column; and

an additional metallization level including a second metallization line in electrical contact with the second metal contact and defining the second bit line for said one column.

27. The integrated circuit of claim 26, wherein the first and second metallization lines extend parallel to the diffusion region, and wherein the polysilicon regions extend perpendicular to the diffusion region.

28. The integrated circuit of claim 26, wherein the first metallization line passes around, without contacting, the second metal contact, and wherein the second metallization line extends over, without contacting, the first metal contact.

29. The integrated circuit of claim 26, wherein the second metallization line extends over the first metallization line.

30. The integrated circuit of claim 21, wherein each row includes a first control gate line and a second control gate line, and wherein the first control gate line is coupled to a gate terminal of the first floating gate transistors of each memory cell in the row and wherein the second control gate line is coupled to a gate terminal of the second floating gate transistors of each memory cell in the row.

31. The integrated circuit of claim 30, further comprising a control circuit coupled to the word line, the first control gate line and the second control gate line, the control circuit configured to apply different control voltages to the first and second control gate lines so as to separately sense a charge retention state of each of the first and second floating gate transistors.