Reducing or eliminating pre-amorphization in transistor manufacture
First Claim
1. A method for forming a plurality of FETs in a substrate, comprising:
- forming at least one PMOS FET; and
forming at least one NMOS FET, the forming at least one NMOS FET includes;
implanting a dopant to form an NMOS anti-punchthrough layer;
implanting a dopant to form an NMOS screen layer;
forming a carbon-containing region above the NMOS screen layer;
forming a diffusion-inhibiting region below the NMOS screen layer using a diffusion-inhibiting material implant, wherein the carbon-containing region and the diffusion-inhibiting region are operable to substantially limit diffusion of the NMOS screen layer dopants;
annealing using a low thermal budget anneal; and
depositing a substantially undoped epitaxial silicon layer on the carbon-containing region; and
forming trench isolation structures to electrically isolate the plurality of FETs from one another.
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Accused Products
Abstract
A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.
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Citations
17 Claims
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1. A method for forming a plurality of FETs in a substrate, comprising:
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forming at least one PMOS FET; and forming at least one NMOS FET, the forming at least one NMOS FET includes; implanting a dopant to form an NMOS anti-punchthrough layer; implanting a dopant to form an NMOS screen layer; forming a carbon-containing region above the NMOS screen layer; forming a diffusion-inhibiting region below the NMOS screen layer using a diffusion-inhibiting material implant, wherein the carbon-containing region and the diffusion-inhibiting region are operable to substantially limit diffusion of the NMOS screen layer dopants; annealing using a low thermal budget anneal; and depositing a substantially undoped epitaxial silicon layer on the carbon-containing region; and forming trench isolation structures to electrically isolate the plurality of FETs from one another. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for forming a plurality of transistor devices in a substrate, the transistor devices each having a defined threshold voltage, the method comprising:
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forming a PMOS field effect transistor (FET) in a first doped well of the substrate, the PMOS FET having a source and a drain, wherein the forming the PMOS FET includes; implanting dopants in the first doped well to form a PMOS anti-punchthrough layer; and implanting dopants in the first doped well to form a PMOS screen layer above the PMOS anti-punchthrough layer, the PMOS screen layer being positioned laterally between eventual positions of the source and the drain; forming an NMOS field effect transistor (FET) in a second doped well of the substrate, the NMOS FET having a source and a drain, wherein forming the NMOS FET includes; implanting dopants in the first doped well to form an NMOS anti-punchthrough layer; forming an NMOS screen layer above the NMOS anti-punchthrough layer, the NMOS screen layer being positioned laterally between eventual positions of the source and the drain; forming an epitaxial carbon-containing silicon layer positioned above the NMOS screen layer, the epitaxial carbon-containing silicon layer being formed as a selective epitaxial layer; and performing an anneal; and forming a plurality of shallow trench isolation structures to define a plurality of transistor regions. - View Dependent Claims (9, 10, 11, 12)
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13. A method for forming an NMOS field effect transistor (FET) in a doped well of a substrate, the NMOS FET having a source and a drain, comprising:
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forming an epitaxial carbon-containing silicon layer in the doped well; implanting dopants to form an NMOS anti-punchthrough layer positioned below the carbon-containing silicon layer; implanting dopants in the epitaxial carbon-containing silicon layer to form an NMOS screen layer above the anti-punchthrough layer, the NMOS screen layer being positioned laterally between eventual positions of the source and the drain; annealing the substrate; implanting dopants in the epitaxial carbon-containing silicon layer to form a threshold voltage set layer above the NMOS screen layer; following implanting of all dopants, depositing a substantially undoped epitaxial silicon material on the epitaxial carbon-containing silicon layer; and forming a gate structure on the epitaxial silicon material. - View Dependent Claims (14, 15, 16, 17)
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Specification