Reducing or eliminating pre-amorphization in transistor manufacture

• US 9,514,940 B2
• Filed: 01/20/2015
• Issued: 12/06/2016
• Est. Priority Date: 05/16/2011
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Scudder, Lance S., Ranade, Pushkar, Stager, Charles, Sridharan, Urupattur C., Zhao, Dalong
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US14/600,865
• Publication Number:
  US 20160268133A1
• Time in Patent Office: 686 Days
• Field of Search: 438/527
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

Claims

1. A method for forming a plurality of FETs in a substrate, comprising:

forming at least one PMOS FET; and

forming at least one NMOS FET, the forming at least one NMOS FET includes;

implanting a dopant to form an NMOS anti-punchthrough layer;

implanting a dopant to form an NMOS screen layer;

forming a carbon-containing region above the NMOS screen layer;

forming a diffusion-inhibiting region below the NMOS screen layer using a diffusion-inhibiting material implant, wherein the carbon-containing region and the diffusion-inhibiting region are operable to substantially limit diffusion of the NMOS screen layer dopants;

annealing using a low thermal budget anneal; and

depositing a substantially undoped epitaxial silicon layer on the carbon-containing region; and

forming trench isolation structures to electrically isolate the plurality of FETs from one another.

2. The method of claim 1, wherein the diffusion-inhibiting region comprises a material selected from the group consisting of carbon and fluorine.

3. The method of claim 2, wherein the carbon is formed using ion implantation.

4. The method of claim 1, wherein annealing includes using solid phase epitaxy at a temperature of between 500 and 800 degrees Celsius.

5. The method of claim 1, wherein annealing includes using a rapid thermal anneal at a temperature of between 900 and 1250 degrees Celsius.

6. The method of claim 1, wherein depositing a substantially undoped epitaxial silicon layer includes using selective epitaxial growth.

7. The method of claim 1, wherein the carbon-containing region is formed using doped epitaxial growth.

8. A method for forming a plurality of transistor devices in a substrate, the transistor devices each having a defined threshold voltage, the method comprising:

forming a PMOS field effect transistor (FET) in a first doped well of the substrate, the PMOS FET having a source and a drain, wherein the forming the PMOS FET includes;

implanting dopants in the first doped well to form a PMOS anti-punchthrough layer; and

implanting dopants in the first doped well to form a PMOS screen layer above the PMOS anti-punchthrough layer, the PMOS screen layer being positioned laterally between eventual positions of the source and the drain;

forming an NMOS field effect transistor (FET) in a second doped well of the substrate, the NMOS FET having a source and a drain, wherein forming the NMOS FET includes;

implanting dopants in the first doped well to form an NMOS anti-punchthrough layer;

forming an NMOS screen layer above the NMOS anti-punchthrough layer, the NMOS screen layer being positioned laterally between eventual positions of the source and the drain;

forming an epitaxial carbon-containing silicon layer positioned above the NMOS screen layer, the epitaxial carbon-containing silicon layer being formed as a selective epitaxial layer; and

performing an anneal; and

forming a plurality of shallow trench isolation structures to define a plurality of transistor regions.

9. The method of claim 8, wherein performing an anneal includes using solid phase epitaxy at a temperature of between 500 and 800 degrees Celsius.

10. The method of claim 8, wherein performing an anneal includes using rapid thermal anneal at a temperature of between 900 and 1250 degrees Celsius.

11. The method of claim 8, further including forming an epitaxial silicon material over the epitaxial carbon-containing silicon layer.

12. The method of claim 11, wherein forming an epitaxial silicon material includes forming a blanket epitaxial silicon layer over each FET.

13. A method for forming an NMOS field effect transistor (FET) in a doped well of a substrate, the NMOS FET having a source and a drain, comprising:

forming an epitaxial carbon-containing silicon layer in the doped well;

implanting dopants to form an NMOS anti-punchthrough layer positioned below the carbon-containing silicon layer;

implanting dopants in the epitaxial carbon-containing silicon layer to form an NMOS screen layer above the anti-punchthrough layer, the NMOS screen layer being positioned laterally between eventual positions of the source and the drain;

annealing the substrate;

implanting dopants in the epitaxial carbon-containing silicon layer to form a threshold voltage set layer above the NMOS screen layer;

following implanting of all dopants, depositing a substantially undoped epitaxial silicon material on the epitaxial carbon-containing silicon layer; and

forming a gate structure on the epitaxial silicon material.

14. The method of claim 13, wherein annealing the substrate includes using solid phase epitaxy at a temperature of between 500 and 800 degrees Celsius.

15. The method of claim 13, wherein annealing the substrate includes using rapid thermal anneal at a temperature of between 900 and 1250 degrees Celsius.

16. The method of claim 13, wherein the epitaxial silicon material is a blanket epitaxial layer over multiple FETs.

17. The method of claim 13, wherein a shallow trench isolation is formed in the substrate.