Electrical connection for chip scale packaging

• US 9,515,038 B2
• Filed: 05/05/2015
• Issued: 12/06/2016
• Est. Priority Date: 06/03/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yew, Ming-Chih, Li, Fu-Jen, Lin, Po-Yao, Cheng, Chia-Jen, Yu, Hsiu-Mei
• Primary Examiner(s): Nguyen, Tram H
• Application Number:
  US14/704,563
• Publication Number:
  US 20150235976A1
• Time in Patent Office: 581 Days
• Field of Search: 257/737, 257/E23.021, 257/738, 257/758, 257/41, 257/81, 257/82, 257/91, 257/99, 257177-182, 257E2301-E23079, 257E23141-E23179, 438/83, 438/98, 438/100, 438/101, 438/111, 438/112, 438/123, 438/124, 438/411, 438/412, 438/461, 438/584, 438597-688
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/02233 not in direct contact with the bonding area
• CPC Class Codes: H01L 2224/02235 Reinforcing structures
• CPC Class Codes: H01L 2224/02255 Shape of the auxiliary member
• CPC Class Codes: H01L 2224/0235 Shape of the redistribution layers
• CPC Class Codes: H01L 2224/02351 comprising interlocking features
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05005 Structure
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/10155 Reinforcing structures
• CPC Class Codes: H01L 2224/13005 Structure
• CPC Class Codes: H01L 2224/13006 Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/2076 : equal to or larger than 100 microns
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/35121 : Peeling or delaminating

Abstract

A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials'"'"' coefficient of thermal expansion.

Claims

1. A semiconductor device comprising:

a first post-passivation interconnect over a substrate, wherein the first post-passivation interconnect comprises a landing pad region, wherein the landing pad region further comprises;

a central region with a first diameter;

a first extension region extending a first distance away from the central region in a first direction;

a second extension region extending a second distance away from the central region in a second direction opposite the first direction;

a third extension region extending a third distance away from the central region in a third direction perpendicular to the first direction; and

a fourth extension region extending a fourth distance away from the central region in a fourth direction opposite the third direction, wherein a first sum of the first diameter, the first distance, and the second distance is greater than a second sum of the first diameter, the third distance, and the fourth distance; and

an underbump metallization over the first post-passivation interconnect, the underbump metallization having an interface in contact with the landing pad region, the interface having a second length that is less than the first sum and the second sum, the underbump metallization having a third length that is less than the first sum and the second sum.

2. The semiconductor device of claim 1, wherein the first distance is between about 0.5 μ

m and about 100 μ

m.

3. The semiconductor device of claim 2, wherein the second distance is equal to the first distance.

4. The semiconductor device of claim 1, further comprising an interconnect region in physical contact with the landing pad region, the interconnect region having a first dimension less than the first sum and the second sum.

5. The semiconductor device of claim 1, further comprising a passivation layer over the first post-passivation interconnect.

6. The semiconductor device of claim 1, further comprising a second post-passivation interconnect over a substrate, wherein the second post-passivation interconnect comprises a second landing pad region, wherein the second landing pad region further comprises:

a second central region with a second diameter;

a fifth extension region extending a fifth distance away from the second central region in a fifth direction;

a sixth extension region extending a sixth distance away from the second central region in a sixth direction opposite the fifth direction;

a seventh extension region extending a seventh distance away from the second central region in a seventh direction perpendicular to the fifth direction; and

an eighth extension region extending a eighth distance away from the second central region in an eighth direction opposite the seventh direction, wherein a third sum of the second diameter, the fifth distance, and the sixth distance is greater than a fourth sum of the second diameter, the seventh distance, and the eighth distance.

7. The semiconductor device of claim 6, wherein the second direction and the sixth direction are both directed towards a middle of the semiconductor device.

8. The semiconductor device of claim 1, wherein the second direction is directed towards a middle of the semiconductor device.

9. A semiconductor device comprising:

a redistribution layer over a substrate, the redistribution layer comprising a landing pad and a first periphery region, the landing pad having a largest dimension in a plan view; and

an underbump metallization in physical contact with the landing pad, the underbump metallization having a largest dimension in the plan view, wherein the largest dimension of the underbump metallization is greater than the largest dimension of the landing pad, the first periphery region underlies an outside edge of the underbump metallization, the first periphery region is electrically isolated, and conductive material of the first periphery region is surrounded by first dielectric material.

10. The semiconductor device of claim 9, wherein the landing pad is a discontinuous conductive material.

11. The semiconductor device of claim 9, wherein the first periphery region is located between about 0.5 μ

m and about 100 μ

m from the landing pad.

12. The semiconductor device of claim 9, wherein the first periphery region is located between about 1 μ

m and about 300 μ

m from a closest portion of an interface between the underbump metallization and the landing pad.

13. The semiconductor device of claim 9, further comprising a second periphery region of conductive material located on an opposite side of the landing pad from the first periphery region, wherein the second periphery region of conductive material underlies the outside edge of the underbump metallization, wherein the second periphery region of conductive material is surrounded by the first dielectric material.

14. The semiconductor device of claim 13, further comprising a third periphery of conductive material region underlying the outside edge of the underbump metallization, wherein the third periphery region of conductive material is surrounded by the first dielectric material.

15. The semiconductor device of claim 9, wherein the first periphery region has a width of between about 3 μ

m and about 300 μ

m.

16. The semiconductor device of claim 15, wherein the first periphery region has a length of between about 3 μ

m and about 300 μ

m.

17. A semiconductor device comprising:

a first post-passivation interconnect over a substrate, wherein the first post-passivation interconnect comprises a first landing pad region with a first length and a first width, wherein the first landing pad region has an elongated shape with a first longitudinal axis;

a first underbump metallization over the first post-passivation interconnect, the first underbump metallization having a first interface in contact with the first landing pad region, the first interface having a second length that is less than the first width and the first length, the first underbump metallization having a third length that is less than the first width and the first length;

a second post-passivation interconnect over the substrate, wherein the second post-passivation interconnect comprises a second landing pad region with a fourth length and a third width, wherein the second landing pad region has an elongated shape with a second longitudinal axis that is not parallel with the first longitudinal axis; and

a second underbump metallization over the second post-passivation interconnect, the second underbump metallization having a second interface in contact with the second landing pad region, the second interface having a fifth length that is less than the third width and the fourth length, the second underbump metallization having a fifth length that is less than the third width and the fourth length.

18. The semiconductor device of claim 17, wherein the first longitudinal axis is aligned with a first direction of coefficient of thermal expansion mismatch.

19. The semiconductor device of claim 18, wherein the second longitudinal axis is aligned with a second direction of coefficient of thermal expansion mismatch.

20. The semiconductor device of claim 19, wherein the first direction of coefficient of thermal expansion mismatch and the second direction of coefficient of thermal expansion mismatch meet each other in a middle of the semiconductor device.