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Electrical connection for chip scale packaging

  • US 9,515,038 B2
  • Filed: 05/05/2015
  • Issued: 12/06/2016
  • Est. Priority Date: 06/03/2011
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • a first post-passivation interconnect over a substrate, wherein the first post-passivation interconnect comprises a landing pad region, wherein the landing pad region further comprises;

    a central region with a first diameter;

    a first extension region extending a first distance away from the central region in a first direction;

    a second extension region extending a second distance away from the central region in a second direction opposite the first direction;

    a third extension region extending a third distance away from the central region in a third direction perpendicular to the first direction; and

    a fourth extension region extending a fourth distance away from the central region in a fourth direction opposite the third direction, wherein a first sum of the first diameter, the first distance, and the second distance is greater than a second sum of the first diameter, the third distance, and the fourth distance; and

    an underbump metallization over the first post-passivation interconnect, the underbump metallization having an interface in contact with the landing pad region, the interface having a second length that is less than the first sum and the second sum, the underbump metallization having a third length that is less than the first sum and the second sum.

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