Driver circuit, method of manufacturing the driver circuit, and display device including the driver circuit

• US 9,515,065 B2
• Filed: 03/03/2015
• Issued: 12/06/2016
• Est. Priority Date: 06/29/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US14/636,264
• Publication Number:
  US 20150243647A1
• Time in Patent Office: 644 Days
• Field of Search: 327108-112, 326/82, 326/83
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2330/04 Display protection
• CPC Class Codes: G09G 3/3283 in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H02H 9/044 Physical layout, materials not provided for elsewhere varistors H01C7/12; spark-gaps H01T; Ovshinsky devices H10N70/00
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 428/24364 with transparent or protective coating
• CPC Class Codes: Y10T 428/24372 Particulate matter
• CPC Class Codes: Y10T 428/2438 Coated

Abstract

Provided are a driver circuit which suppresses damage of a semiconductor element due to ESD in a manufacturing process, a method of manufacturing the driver circuit. Further provided are a driver circuit provided with a protection circuit with low leakage current, and a method of manufacturing the driver circuit. By providing a protection circuit in a driver circuit to be electrically connected to a semiconductor element in the driver circuit, and by forming, at the same time, a transistor which serves as the semiconductor element in the driver circuit and a transistor included in the protection circuit in the driver circuit, damage of the semiconductor element due to ESD is suppressed in the process of manufacturing the driver circuit. Further, by using an oxide semiconductor film for the transistor included in the protection circuit in the driver circuit, leakage current in the protection circuit is reduced.

Claims

1. A display device comprising:

a first transistor in a pixel portion over a substrate;

a driver circuit over the substrate and electrically connected to the first transistor;

a protection circuit electrically connected to the driver circuit, the protection circuit comprising a second transistor, wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer over the substrate, a gate insulating film over the oxide semiconductor layer and a gate electrode over the gate insulating film, the oxide semiconductor layer comprising a source region, a drain region and a channel formation region between the source region and the drain region; and

a pixel electrode electrically connected to one of the source region and the drain region of the first transistor,

wherein the source region and the drain region have a lower resistance than the channel formation region, and

wherein the gate electrode of the second transistor is electrically connected to one of the source region and the drain region of the second transistor.

2. The display device according to claim 1, wherein the source region and the drain region are doped with a metal element.

3. The display device according to claim 1, wherein the source region and the drain region are doped with an impurity.

4. The display device according to claim 1, wherein the oxide semiconductor layer is formed on an insulating film having an average surface roughness of less than or equal to 1 nm.

5. The display device according to claim 1, wherein the oxide semiconductor layer has a crystallinity.

6. A display device comprising:

a first transistor in a pixel portion over a substrate;

a driver circuit over the substrate and electrically connected to the first transistor;

a protection circuit electrically connected to the driver circuit, the protection circuit comprising a second transistor, wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer over the substrate, a gate insulating film over the oxide semiconductor layer and a gate electrode over the gate insulating film, the oxide semiconductor layer comprising a source region, a drain region, a channel formation region between the source region and the drain region, a first impurity region between the channel formation region and the source region, and a second impurity region between the channel formation region and the drain region; and

a pixel electrode electrically connected to one of the source region and the drain region of the first transistor,

wherein the source region and the drain region have a lower resistance than the channel formation region,

wherein the first impurity region and the second impurity region have a lower resistance than the channel formation region, and

wherein the gate electrode of the second transistor is electrically connected to one of the source region and the drain region of the second transistor.

7. The display device according to claim 6, wherein the source region and the drain region are doped with a metal element.

8. The display device according to claim 6, wherein the source region and the drain region are doped with an impurity.

9. The display device according to claim 6, wherein the oxide semiconductor layer is formed on an insulating film having an average surface roughness of less than or equal to 1 nm.

10. The display device according to claim 6, wherein the oxide semiconductor layer has a crystallinity.

11. A display device comprising:

a first transistor in a pixel portion over a substrate;

a power supply line over the substrate;

a protection circuit electrically connected to the power supply line, the protection circuit comprising a second transistor, wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer over the substrate, a gate insulating film over the oxide semiconductor layer and a gate electrode over the gate insulating film, the oxide semiconductor layer comprising a source region, a drain region and a channel formation region between the source region and the drain region; and

a pixel electrode electrically connected to one of the source region and the drain region of the first transistor,

wherein the source region and the drain region have a lower resistance than the channel formation region, and

wherein the gate electrode of the second transistor is electrically connected to one of the source region and the drain region of the second transistor.

12. The display device according to claim 11, wherein the source region and the drain region are doped with a metal element.

13. The display device according to claim 11, wherein the source region and the drain region are doped with an impurity.

14. The display device according to claim 11, wherein the oxide semiconductor layer is formed on an insulating film having an average surface roughness of less than or equal to 1 nm.

15. The display device according to claim 11, wherein the oxide semiconductor layer has a crystallinity.