3D nonvolatile memory device having common word line

• US 9,515,084 B2
• Filed: 03/24/2015
• Issued: 12/06/2016
• Est. Priority Date: 10/17/2014
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Oh, Sung Lae, Kim, Jin Ho
• Primary Examiner(s): Ingham, John C
• Assistant Examiner(s): MAZUMDER, DIDARUL A
• Application Number:
  US14/667,397
• Publication Number:
  US 20160111361A1
• Time in Patent Office: 623 Days
• Field of Search: 257/390
• US Class Current: 1/1
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A 3D nonvolatile memory device including memory cells vertically stacked is disclosed. Word lines are integrally formed to be elongated over adjacent cell regions spaced apart from each other, and portions of the word lines between the cell regions are partially etched in a stepped shape to form word line contact regions.

Claims

1. A three-dimensional (3D) nonvolatile memory device comprising:

a first cell region;

a second cell region spaced apart from the first cell region; and

a stack of common word lines extending from the first cell region to the second cell region and physically connected to the first cell region and the second cell region,

wherein the stack of common word lines includes N number of common word lines, where N is an integer,

wherein the stack of common word lines includes a first slim region,

wherein the first slim region has a stepped structure and is located between the first cell region and the second cell region.

2. The 3D nonvolatile memory device of claim 1, further comprising:

M number of pass transistors located under the stack of common word lines,

wherein the pass transistors include a first junction region coupled to the stack of common word lines and a second junction region coupled to a global word line.

3. The 3D nonvolatile memory device of claim 2,

wherein the first junction region is located in a slit region and provided between the stack of common word lines and a neighboring stack of common word lines.

4. The 3D nonvolatile memory device of claim 3, further comprising:

a first contact located in the slit region and configured to electrically couple the first junction region to the L^th common word line, where L is an integer and 1≦

L≦

N.

5. The 3D nonvolatile memory device of claim 1,

wherein X number of common word lines are exposed in the first slim region,

wherein the X number of common word lines form a stepped structure in the first slim region, and

where X is an integer and 1≦

X≦

N.

6. The 3D nonvolatile memory device of claim 5,

wherein the first slim region is located between the first cell region and the second cell region, and the stack of common word lines extends from the first cell region through the first slim region to the second cell region.

7. The 3D nonvolatile memory device of claim 6.

wherein the stack of common word lines further includes a second slim region,

wherein the first slim region is located at a first sidewall of the stack of common word lines,

wherein the second slim region is located at a second sidewall of the stack of common word lines,

wherein the second sidewall is located opposite to the first sidewall,

wherein the first cell region is located at a third sidewall of the stack of common word lines,

wherein the second cell region is located at a fourth sidewall of the stack of common word lines,

wherein the third sidewall is located opposite to the fourth sidewall,

wherein the first cell region and the second cell are arranged in a first direction,

wherein the first slim region and the second slim region are arranged in a second direction, and

wherein the second direction is different from the first direction.

8. The 3D nonvolatile memory device of claim 7,

wherein the first slim region is located closer to the first cell region than the second cell region, and

wherein the second slim region is located between the first cell region and the second cell region, and is closer to the second cell region than the first cell region.

9. The 3D nonvolatile memory device of claim 7,

wherein Y number of common word lines are exposed in the second slim region, and the Y number of common word lines form a stepped structure in the second slim region, where Y is an integer and 1≦

Y≦

N.

10. The 3D nonvolatile memory device of claim 9,

wherein N−

X=Y, and each of the X number of common word lines and each of the Y number of common word lines are different from each other.

11. The 3D nonvolatile memory device of claim 6,

wherein the first slim region is located in a first sidewall of the stack of common word lines, and the first slim region includes a plurality of slim regions.

12. The 3D nonvolatile memory device of claim 1,

wherein the stack of common word lines includes E number of slim regions,

wherein the N number common word lines are divided into the E number of groups, and

wherein the E number of groups correspond to the E number of slim regions, respectively, and are exposed by their respective slim regions, where E is an integer and 1≦

E≦

N.