Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors

• US 9,515,173 B2
• Filed: 12/22/2015
• Issued: 12/06/2016
• Est. Priority Date: 07/15/2014
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Hashemi, Pouya, Khakifirooz, Ali, Reznicek, Alexander
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US14/979,195
• Publication Number:
  US 20160111544A1
• Time in Patent Office: 350 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/056 : the transistor being a FinFET

Abstract

Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate.

Claims

1. A method of forming a semiconductor structure comprising:

providing a semiconductor-containing fin structure on a surface of a base layer, wherein said semiconductor-containing fin structure comprises, from bottom to top, and in an alternating manner, at least one first semiconductor material portion having a first oxidation rate, and at least one second semiconductor material portion having a second oxidation rate, wherein said first oxidation rate is slower than the second oxidation rate;

performing an oxidation process to form an oxide liner portion on each of said first semiconductor material portions and to completely convert each of said second semiconductor material portions into an oxide structure;

completely removing said first oxide liner portion from each of said first semiconductor material portions and each of said oxide structures; and

epitaxially growing a semiconductor material protruding portion from an exposed semiconductor sidewall surface of each of said first semiconductor material portions.

2. The method of claim 1, further comprising forming a gate structure surrounding said semiconductor-containing fin structure, wherein said gate structure comprises a gate dielectric material portion and a gate electrode material portion.

3. The method of claim 1, wherein said providing the semiconductor-containing fin structure comprises:

providing a semiconductor-containing layer of a first semiconductor material on said surface of said base layer;

forming an initial second semiconductor material on said semiconductor-containing layer, wherein said first semiconductor material has said slower oxidation rate than said second semiconductor material;

forming a hard mask material atop said initial second semiconductor layer; and

patterning.

4. The method of claim 3, further comprising forming alternating layers of said first semiconductor material and said second semiconductor material on said initial second semiconductor material.

5. The method of claim 1, wherein each of said semiconductor material protruding portions has a shape of a triangular and wherein a base of said triangular is formed directly on said exposed semiconductor sidewall surface of each of said least one first semiconductor material portions.