Semiconductor device

• US 9,515,192 B2
• Filed: 09/09/2015
• Issued: 12/06/2016
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Hosoba, Miyuki, Sakata, Junichiro, Kuwabara, Hideaki
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US14/848,492
• Publication Number:
  US 20160005875A1
• Time in Patent Office: 454 Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/167 by electrophoresis
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/344 based on particles moving in a fluid or in a gas, e.g. electrophoretic devices electrophoretic devices per se G02F1/167
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1274 using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 29/45 : Ohmic electrodes
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 : of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/786 : Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78606 : with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs

Abstract

An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

Claims

1. A semiconductor device comprising:

a substrate;

a gate electrode over the substrate;

a first inorganic insulating layer over the gate electrode and the substrate;

a first oxide insulating layer over the first inorganic insulating layer;

an oxide semiconductor layer on and in direct contact with the first oxide insulating layer;

a second oxide insulating layer on and in direct contact with a channel formation region of the oxide semiconductor layer and overlapping with the gate electrode;

a source electrode layer and a drain electrode layer on and in direct contact with a first region and a second region of the oxide semiconductor layer, respectively,

a second inorganic insulating layer over the second oxide insulating layer, on and in direct contact with side edges of the second oxide insulating layer, and on and in direct contact with a third region and a fourth region of the oxide semiconductor layer, the third region being between the channel formation region and one of the first region and the second region, and the fourth region being between the channel formation region and the other of the first region and the second region;

a third inorganic insulating layer over the second inorganic insulating layer;

an organic insulating layer over the third inorganic insulating layer; and

a pixel electrode layer over the organic insulating layer and on and in electrical contact with one of the source electrode layer and the drain electrode layer.

2. The semiconductor device according to claim 1, wherein each of the first to the third inorganic insulating layers and each of the first and the second oxide insulating layers comprises silicon and at least one of oxygen and nitrogen.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is in a pixel portion.

4. The semiconductor device according to claim 1, wherein the second and the third inorganic insulating layers are over the source electrode layer and the drain electrode layer.

5. The semiconductor device according to claim 1, wherein the second inorganic insulating layer further comprises oxygen.

6. The semiconductor device according to claim 1, wherein the source electrode layer and the drain electrode layer comprise copper.

7. The semiconductor device according to claim 1, further comprising a flexible printed circuit affixed to the substrate.

8. A semiconductor device comprising:

a substrate;

a gate electrode over the substrate;

a first inorganic insulating layer over the gate electrode and the substrate;

a first oxide insulating layer over the first inorganic insulating layer;

an oxide semiconductor layer on and in direct contact with the first oxide insulating layer;

a second oxide insulating layer on and in direct contact with a channel formation region of the oxide semiconductor layer and overlapping with the gate electrode;

a source electrode layer and a drain electrode layer on and in direct contact with a first region and a second region of the oxide semiconductor layer, respectively,

a second inorganic insulating layer over the second oxide insulating layer, on and in direct contact with side edges of the second oxide insulating layer, and on and in direct contact with a third region and a fourth region of the oxide semiconductor layer, the third region being between the channel formation region and one of the first region and the second region, and the fourth region being between the channel formation region and the other of the first region and the second region;

a third inorganic insulating layer over the second inorganic insulating layer;

an organic insulating layer over the third inorganic insulating layer; and

a pixel electrode layer over the organic insulating layer and on and in electrical contact with one of the source electrode layer and the drain electrode layer,

wherein the first inorganic insulating layer comprises silicon and nitrogen,

wherein the first oxide insulating layer comprises silicon and oxygen,

wherein the second oxide insulating layer comprises silicon, oxygen, and nitrogen,

wherein the second inorganic insulating layer comprises silicon and nitrogen, and

wherein the third inorganic insulating layer comprises silicon, nitrogen, and oxygen.

9. The semiconductor device according to claim 8, wherein the oxide semiconductor layer is in a pixel portion.

10. The semiconductor device according to claim 8, wherein the second and the third inorganic insulating layers are over the source electrode layer and the drain electrode layer.

11. The semiconductor device according to claim 8, wherein the second inorganic insulating layer further comprises oxygen.

12. The semiconductor device according to claim 8, wherein the source electrode layer and the drain electrode layer comprise copper.

13. The semiconductor device according to claim 8, further comprising a flexible printed circuit affixed to the substrate.

14. A semiconductor device comprising:

a substrate;

a first gate electrode over the substrate;

a first inorganic insulating layer over the first gate electrode and the substrate;

a first oxide insulating layer over the first inorganic insulating layer;

an oxide semiconductor layer on and in direct contact with the first oxide insulating layer;

a second oxide insulating layer on and in direct contact with a channel formation region of the oxide semiconductor layer and overlapping with the first gate electrode;

a source electrode layer and a drain electrode layer on and in direct contact with a first region and a second region of the oxide semiconductor layer, respectively,

a second inorganic insulating layer over the second oxide insulating layer, on and in direct contact with side edges of the second oxide insulating layer, and on and in direct contact with a third region and a fourth region of the oxide semiconductor layer, the third region being between the channel formation region and one of the first region and the second region, and the fourth region being between the channel formation region and the other of the first region and the second region;

a third inorganic insulating layer over the second inorganic insulating layer;

an organic insulating layer over the third inorganic insulating layer;

a second gate electrode over the oxide semiconductor layer and overlapping with the first gate electrode; and

a pixel electrode layer over the organic insulating layer and on and in electrical contact with one of the source electrode layer and the drain electrode layer,

wherein the first inorganic insulating layer comprises silicon and nitrogen and is in direct contact with the first gate electrode,

wherein the first oxide insulating layer comprises silicon and oxygen and is in direct contact with the first inorganic insulating layer,

wherein the second oxide insulating layer comprises silicon, oxygen, and nitrogen,

wherein the second inorganic insulating layer comprises silicon and nitrogen, and

wherein the third inorganic insulating layer comprises silicon, nitrogen, and oxygen and is in direct contact with the second inorganic insulating layer.

15. The semiconductor device according to claim 14, wherein the second gate electrode is over the organic insulating layer.

16. The semiconductor device according to claim 14, wherein the oxide semiconductor layer is in a drive circuit.

17. The semiconductor device according to claim 14, wherein the second and the third inorganic insulating layers are over the source electrode layer and the drain electrode layer.

18. The semiconductor device according to claim 14, wherein the second inorganic insulating layer further comprises oxygen.

19. The semiconductor device according to claim 14, wherein the source electrode layer and the drain electrode layer comprise copper.

20. The semiconductor device according to claim 14, further comprising a flexible printed circuit affixed to the substrate.