Power-on reset circuit

• US 9,515,637 B1
• Filed: 09/03/2015
• Issued: 12/06/2016
• Est. Priority Date: 08/24/2015
• Status: Active Grant

• Current Assignee: RUIZHANG TECHNOLOGY LIMITED COMPANY
• Original Assignee: RUIZHANG TECHNOLOGY LIMITED COMPANY
• Inventors: Schnaitter, William, Wang, Steve
• Primary Examiner(s): Puentes, Daniel
• Application Number:
  US14/845,246
• Time in Patent Office: 460 Days
• US Class Current: 1/1
• CPC Class Codes: H03K 17/22 Modifications for ensuring a predetermined initial state when the supply voltage has been applied bi-stable generators H03K3/12
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 5/24 the characteristic being amplitude

Abstract

A Power-on Reset circuit is described. The Power-on Reset is formed by two comparators and a latch circuit. The Power-on Reset circuit will de-assert the reset state once the supply voltage reaches a first reference point and re-assert the reset state once the supply voltage drops below a second reference point. The Power-on Reset circuit disclosed further includes circuits to initialize properly and to ensure the regulator voltage and the bandgap voltages are stable and above the ground level voltage.

Claims

1. A power-on reset circuit that generates a reset signal, comprising:

a first comparator having a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to a first reference voltage, and the second input terminal coupled to a supply voltage;

a second comparator having a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to the supply voltage, and the second input terminal coupled to a second reference voltage;

a latch circuit having a first terminal, a second terminal, and an output, wherein the output terminal of the first comparator is coupled to the first terminal, the output terminal of the second comparator is coupled to the second terminal, and the output of the latch circuit is configured to generate a de-assert signal to de-assert a reset state in response to the supply voltage increasing above the first reference voltage and is configured to generate a re-assert signal to re-assert the reset state in response to the supply voltage dropping below the second reference voltage; and

a blocking circuit that blocks the de-assert signal prior to the reference voltages stabilizing.

2. The power-on reset circuit of claim 1, wherein the first reference voltage is greater than the second reference voltage.

3. The power-on reset circuit of claim 2, wherein the first reference voltage and the second reference voltage are proportional to a regulator voltage and the regulator voltage is generated based on a bandgap voltage.

4. The power-on reset circuit of claim 1, wherein prior to the latch circuit generating the de-assert signal the reset state is asserted.

5. The power-on reset circuit of claim 4 further comprising a capacitor coupled between the supply voltage and the first terminal of the latch circuit.

6. The power-on reset circuit of claim 5 further comprising a startup circuit, comprising:

a first capacitor coupled between the supply voltage and a first transistor;

the first transistor having a drain coupled to the first capacitor, a source being grounded, and a gate coupled to a control voltage;

a second transistor having a drain coupled to the first terminal of the latch circuit, a source being grounded, and a gate coupled to the source of the first transistor; and

a second capacitor coupled between the first terminal of the latch circuit and the ground.

7. The power-on reset circuit of claim 3, wherein the de-assert signal is configured to be delayed until the regulator voltage is stabilized.

8. The power-on reset circuit of claim 7, wherein a delayed version of the regulator voltage is compared to the regulator voltage.

9. The power-on reset circuit of claim 8, wherein the blocking circuit includes a first de-assert blocking circuit, comprising:

a first transistor having a source coupled to the regulator voltage, a gate coupled to a gate of the second transistor, and a drain coupled to the gate and a third transistor;

a second transistor having a source coupled to the regulator voltage, a gate coupled to the gate of the first transistor, and a drain coupled to a capacitor;

a third transistor having a drain coupled to the drain of the first transistor, a source being grounded, and a gate coupled to a control voltage;

a capacitor coupled between the drain of the second transistor and a ground; and

a comparator having a non-inverting terminal coupled to the regulator voltage and an inverting terminal coupled to the drain of the second transistor.

10. The power-on reset circuit of claim 9 wherein a size of the capacitor determine a delay time for generating the delayed version of the regulator voltage.

11. The power-on reset circuit of claim 3, wherein the de-assert signal is configured to be delayed until the regulator voltage is stabilized.

12. The power-on reset circuit of claim 3, wherein the de-assert signal is configured to be delayed until the regulator voltage is substantially above a ground voltage.

13. The power-on reset circuit of claim 12, wherein the blocking circuit includes a second de-assert blocking circuit, comprising:

a first transistor having a source coupled to the supply voltage, a gate coupled to a gate of the second transistor, and a drain coupled to the gate and a third transistor;

a second transistor having a source coupled to the supply voltage, a gate coupled to the gate of the first transistor, and a drain coupled to a fourth transistor;

a third transistor having a drain coupled to the source of the first transistor, a source being grounded, and a gate coupled to a control voltage;

a fourth transistor having a drain coupled to the drain of the second transistor, a source being grounded, and a gate coupled to a voltage divider;

the voltage divider coupled to the regulator voltage and a ground;

a capacitor coupled between the power supply and the drain of the second transistor; and

an output signal generated at a terminal coupling the drain of the second transistor and the source of the fourth transistor.

14. The power-on reset circuit of claim 13, wherein the voltage divider defines a range for the regulator voltage above the ground to allow generating the de-assert signal.

15. The power-on reset circuit of claim 3, wherein the second reference voltage is a stored version of the regulator voltage.

16. The power-on reset circuit of claim 15 further comprising a delay circuit, comprising:

a transistor having a drain coupled to the regulator voltage, a gate coupled to the supply voltage, and a source coupled to a capacitor,

wherein the second input terminal of the second comparator is coupled to the source of the transistor.

17. The power-on reset circuit of claim 3, wherein after the generating of the de-assert signal the first reference signal is changed to a different voltage level.

18. The power-on reset circuit of claim 17 further comprising:

a series of resistors coupled between the regulator voltage and a first transistor;

the first transistor having a drain connected to the series of resistors, a source coupled to second transistor, and a gate coupled to an enabling signal;

the second transistor having a drain coupled to the source of the first transistor, a gate coupled to a control voltage, and a source being grounded,

wherein the first input terminal of the first comparator is coupled to a terminal between the series of resistors.

19. An apparatus for generating a power-on reset signal comprising:

means for comparing a first reference voltage and a supply voltage;

means for comparing a second reference voltage and the supply voltage;

means for generating a de-assert signal to de-assert a reset state in response to the supply voltage increasing above the first reference voltage;

means for generating a re-assert signal to re-assert the reset state in response to the supply voltage dropping below the second reference voltage; and

means for blocking the de-assert signal prior to the reference voltages stabilizing.

20. The apparatus of claim 19, wherein the first reference voltage is greater than the second referenced voltage.

21. The apparatus of claim 20, wherein the first reference voltage and the second referenced voltage are proportional to a bandgap voltage.

22. The apparatus of claim 19, wherein before generating the de-assert signal the power-on reset signal asserts the reset state.

23. The apparatus of claim 19, wherein the second reference voltage is a stored multiple of a bandgap voltage.

24. An apparatus for generating a power-on reset signal comprising:

means for comparing a first reference voltage and a supply voltage;

means for comparing a second reference voltage and the supply voltage;

means for generating a de-assert signal to de-assert a reset state in response to the supply voltage increasing above the first reference voltage;

means for generating a re-assert signal to re-assert the reset state in response to the supply voltage dropping below the second reference voltage; and

means for blocking the de-assert signal until the bandgap voltage is stabilized.

25. An apparatus for generating a power-on reset signal comprising:

means for comparing a first reference voltage and a supply voltage;

means for comparing a second reference voltage and the supply voltage;

means for generating a de-assert signal to de-assert a reset state in response to the supply voltage increasing above the first reference voltage;

means for generating a re-assert signal to re-assert the reset state in response to the supply voltage dropping below the second reference voltage; and

means for blocking the de-assert signal when the bandgap voltage is substantially at a ground level.