Interface circuit operating to recover error of transmitted data
First Claim
1. An interface circuit configured to transmit and receive data, the interface circuit comprising:
- an encoder configured to encode input data to generate transmission data;
a data sequence detector configured to count a number of successively same logic values in a data string of the transmission data to detect whether the number of the successively same logic values in the data string of the transmission data is equal to or greater than a reference succession number;
a recovery section configured to control, based on a detection result of the data sequence detector, a recovery operation with respect to the transmission data; and
a transmitter configured to output the transmission data.
1 Assignment
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Accused Products
Abstract
Provided is an interface circuit for transmitting and receiving data according to a communication protocol. The interface circuit includes: an encoder configured to encode input data to generate transmission data; a transmitter configured to output the transmission data; a data sequence detector configured to detect whether the number of successively same logic values in a data string of the transmission data is equal to or greater than a reference succession number; and a recovery section configured to control a recovery operation with respect to the transmission data, based on a detection result of the data sequence detector. With the interface circuit, data loss is prevented and data reliability is guaranteed.
25 Citations
20 Claims
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1. An interface circuit configured to transmit and receive data, the interface circuit comprising:
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an encoder configured to encode input data to generate transmission data; a data sequence detector configured to count a number of successively same logic values in a data string of the transmission data to detect whether the number of the successively same logic values in the data string of the transmission data is equal to or greater than a reference succession number; a recovery section configured to control, based on a detection result of the data sequence detector, a recovery operation with respect to the transmission data; and a transmitter configured to output the transmission data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An interface circuit configured to transmit and receive data according to a peripheral component interconnect express (PCIe) protocol, the interface circuit comprising:
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a lane encoder configured to encode input data with a first encoding method of the PCIe protocol to generate transmission data; a data sequence detector configured to detect whether a number of successively same logic values in a data string of the transmission data is equal to or greater than a reference succession number; a link training and status state machine (LTSSM) configured to control, based on a detection result of the data sequence detector, a recovery operation with respect to the transmission data; and a transmitter configured to output the transmission data. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method of generating transmission data, the method comprising:
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encoding, by a transmitting device, input data to generate transmission data; detecting, by the transmitting device, whether a data string of the transmission data sufficiently transits to extract clock information based on whether a number of successively same logic values in the data string of the transmission data is equal to or greater than a reference succession number; and determining, by the transmitting device, whether to perform a recovery operation with respect to the transmission data, based on a result of the detecting. - View Dependent Claims (18, 19, 20)
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Specification