Demodulators for near field communication, near field communication devices, and electronic devices having the same

• US 9,515,702 B2
• Filed: 06/16/2015
• Issued: 12/06/2016
• Est. Priority Date: 11/12/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Jong-Pil, Na, Ji-Myung, Song, Il-jong
• Primary Examiner(s): LE, NHAN T
• Application Number:
  US14/741,321
• Publication Number:
  US 20160134333A1
• Time in Patent Office: 539 Days
• Field of Search: 455/41, 455/1, 455/41.2, 455/41.3, 455/550.1, 455/556.1, 455/557, 455/333
• US Class Current: 1/1
• CPC Class Codes: H03D 1/10 of diodes
• CPC Class Codes: H03D 1/12 with provision for equalising ac and dc loads
• CPC Class Codes: H03D 1/22 Homodyne or synchrodyne circuits receiver circuits H04B1/30
• CPC Class Codes: H04B 5/24 Inductive coupling
• CPC Class Codes: H04B 5/45 Transponders
• CPC Class Codes: H04B 5/72 for local intradevice communication

Abstract

A demodulator for near field communication may include: a scale down circuit configured to receive first and second modulated signals from first and second power electrodes, and configured to provide a scale down signal to a first node by scaling down magnitudes of the first and second modulated signals; a current source coupled between the first node and a ground voltage, and configured to generate a constant current flowing from the first node to the ground voltage; a charge store circuit coupled between the first node and ground voltage, and configured to perform charge and discharge operations alternately, based on the scale down signal and constant current, to output an envelope signal, which corresponds to an envelope of the scale down signal; and/or an edge detector configured to generate input data, which correspond to the first and second modulated signals, based on a transition of the envelope signal.

Claims

1. A demodulator for near field communication (NFC), the demodulator comprising:

a scale down circuit configured to receive a first modulated signal and a second modulated signal from a first power electrode and a second power electrode, respectively, and configured to provide a scale down signal to a first node by scaling down a magnitude of the first modulated signal and a magnitude of the second modulated signal;

a current source coupled between the first node and a ground voltage, and configured to generate a constant current flowing from the first node to the ground voltage;

a charge store circuit coupled between the first node and the ground voltage, and configured to perform a charge operation and a discharge operation alternately, based on the scale down signal and the constant current, to output an envelope signal, which corresponds to an envelope of the scale down signal, through the first node; and

an edge detector configured to generate input data, which correspond to the first modulated signal and the second modulated signal, based on a transition of the envelope signal.

2. The demodulator of claim 1, further comprising:

a voltage clamp circuit configured to generate the first modulated signal and the second modulated signal by clamping a first antenna voltage and a second antenna voltage received from outside of the demodulator through the first power electrode and the second power electrode, respectively.

3. The demodulator of claim 2, wherein the voltage clamp circuit comprises:

a first diode coupled between the first power electrode and the ground voltage; and

a second diode coupled between the second power electrode and the ground voltage.

4. The demodulator of claim 1, wherein the magnitude of the first modulated signal is the same as the magnitude of the second modulated signal, and

wherein a phase of the first modulated signal is different from a phase of the second modulated signal by 180 degrees.

5. The demodulator of claim 1, wherein the scale down circuit is further configured to generate the scale down signal by scaling down the magnitude of the first modulated signal and the magnitude of the second modulated signal by a same ratio.

6. The demodulator of claim 1, wherein the scale down circuit is further configured to generate the scale down signal by scaling down the magnitude of the first modulated signal and the magnitude of the second modulated signal by one half.

7. The demodulator of claim 1, wherein the scale down circuit comprises:

a first resistor coupled between the first power electrode and the first node; and

a second resistor coupled between the second power electrode and the first node.

8. The demodulator of claim 7, wherein a resistance of the first resistor is the same as a resistance of the second resistor.

9. The demodulator of claim 1, wherein the charge store circuit comprises:

a capacitor coupled between the first node and the ground voltage.

10. The demodulator of claim 1, further comprising:

a rectification circuit configured to receive the first modulated signal and the second modulated signal from the first power electrode and the second power electrode, respectively, and configured to provide a rectified signal to the first node by rectifying the first modulated signal and the second modulated signal.

11. The demodulator of claim 10, wherein the rectification circuit comprises:

a first diode coupled between the first power electrode and the first node; and

a second diode coupled between the second power electrode and the first node.

12. The demodulator of claim 11, wherein a threshold voltage of the first diode is the same as a threshold voltage of the second diode.

13. The demodulator of claim 1, further comprising:

a bias circuit coupled to the first power electrode, the second power electrode, and the ground voltage;

wherein the bias circuit is configured to provide bias voltage corresponding to the ground voltage to the first power electrode and the second power electrode.

14. The demodulator of claim 13, wherein the bias circuit comprises:

a first n-type metal oxide semiconductor (NMOS) transistor having a drain coupled to the first power electrode, a source coupled to the ground voltage, and a gate coupled to the second power electrode; and

a second NMOS transistor having a drain coupled to the second power electrode, a source coupled to the ground voltage, and a gate coupled to the first power electrode.

15. A demodulator, comprising:

a circuit configured to receive a first modulated signal from a first power electrode, configured to receive a second modulated signal from a second power electrode, configured to provide a scale down signal to a first node by scaling down a magnitude of the first modulated signal and a magnitude of the second modulated signal, configured to cause a constant current to flow from the first node to a ground voltage, configured to output an envelope signal, corresponding to an envelope of the scale down signal, through the first node, and configured to generate input data based on a transition of the envelope signal.

16. The demodulator of claim 15, wherein the circuit is further configured to alternately perform charging and discharging operations.

17. The demodulator of claim 16, wherein the charging operations are based on the scale down signal.

18. The demodulator of claim 16, wherein the charging operations are based on the constant current.

19. The demodulator of claim 16, wherein the discharging operations are based on the scale down signal.

20. The demodulator of claim 16, wherein the discharging operations are based on the constant current.