Stable probing-resilient physically unclonable function (PUF) circuit

• US 9,515,835 B2
• Filed: 03/24/2015
• Issued: 12/06/2016
• Est. Priority Date: 03/24/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mathew, Sanu K., Satpathy, Sudhir K.
• Primary Examiner(s): LE, DON P
• Application Number:
  US14/667,665
• Publication Number:
  US 20160285639A1
• Time in Patent Office: 623 Days
• Field of Search: 326/8
• US Class Current: 1/1
• CPC Class Codes: G06Q 10/08 Logistics, e.g. warehousing, loading or distribution; Inventory or stock management
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H03K 19/17768 for security
• CPC Class Codes: H04L 2209/04 Masking or blinding
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/3278 using physically unclonable functions [PUF]

Abstract

Embodiments include apparatuses, methods, and systems for a physically unclonable function (PUF) circuit. The PUF circuit may include an array of PUF cells to generate respective PUF bits of an encryption code. Individual PUF cells may include first and second inverters cross-coupled between a bit node and a bit bar node. The individual PUF cells may further include a first pre-charge transistor coupled to the bit node and configured to receive a clock signal via a first clock path, and a second pre-charge transistor coupled to the bit bar node and configured to receive the clock signal via a second clock path. Features and techniques of the PUF cells are disclosed to improve the stability and/or bias strength of the PUF cells, to generate a dark bit mask for the array of PUF cells, and to improve resilience to probing attacks. Other embodiments may be described and claimed.

Claims

1. A physically unclonable function (PUF) circuit comprising:

a bit node and a bit bar node;

a first inverter and a second inverter that are cross-coupled between the bit node and the bit bar node;

a first pre-charge transistor coupled between the bit node and a power supply rail;

a second pre-charge transistor coupled between the bit bar node and the power supply rail, the first and second pre-charge transistors to receive a clock signal via respective first and second clock paths;

a first delay chain disposed on the first clock path;

a second delay chain disposed on the second clock path; and

control circuitry to;

pass the clock signal to the first and second pre-charge transistors during a bit generation mode to generate a PUF bit at the bit node with a first value; and

write a second value to the bit node during a delay hardening mode, the second value being a logical inverse of the first value to provide a differential delay in the first and second clock paths.

2. The PUF circuit of claim 1, further comprising a flip-flop coupled to the bit node to store the first value of the PUF bit, wherein an output terminal of the flip-flop is coupled to the control circuitry.

3. The PUF circuit of claim 2, further comprising a clock terminal to receive the clock signal and an enable terminal to receive an enable signal to switch the PUF circuit between the bit generation mode and the delay hardening mode.

4. The PUF circuit of claim 3, wherein the control circuitry includes:

a first negative-AND (NAND) gate having a first input terminal coupled to the clock terminal to receive the clock signal, a second input terminal coupled to the enable terminal to receive the enable signal, and an output terminal;

a second NAND gate having a first input terminal coupled to receive an inverse of the enable signal, a second input terminal coupled to an output terminal of the flip-flop to receive an output signal, and an output terminal; and

a third NAND gate having a first input terminal coupled to the output terminal of the first NAND gate, a second input terminal coupled to the output terminal of the second NAND gate, and an output terminal coupled to the first delay chain.

5. The PUF circuit of claim 4, further comprising:

a fourth NAND gate having a first input terminal coupled to receive an inverse of the enable signal, a second input terminal coupled to an output bar terminal of the flip-flop to receive an output bar signal, and an output terminal; and

a fifth NAND gate having a first input terminal coupled to the output terminal of the first NAND gate, a second input terminal coupled to the output terminal of the fourth NAND gate, and an output terminal coupled to the second delay chain.

6. The PUF circuit of claim 1, further comprising:

a footer transistor coupled between a first n-type metal-oxide-semiconductor (NMOS) transistor of the first inverter and a ground terminal and between a second NMOS transistor of the second inverter and the ground terminal, the footer transistor to turn off during a pre-charge portion of a bit generation process.

7. The PUF circuit of claim 1, wherein, to write the second value to the bit node during the delay hardening mode, the control circuitry is to pass a voltage corresponding to the second value to the first pre-charge transistor via the first delay chain and is to pass a voltage corresponding to the first value to the second pre-charge transistor via the second delay chain.

8. The PUF circuit of claim 1, wherein the first and second delay chains are programmable delay chains, and wherein the PUF circuit further includes mask generation circuitry coupled to the first and second delay chains to:

control the first and second delay chains to provide a series of different values of a differential delay between the first and second delay chains, wherein the PUF circuit is to perform a bit generation process for each value of the differential delay to generate respective output bits;

determine a bias strength of the PUF circuit based on the output bits; and

generate a dark bit mask based on the determined bias strength.

9. The PUF circuit of claim 8, wherein the mask generation circuitry is to mark the PUF circuit as a dark bit if the determined bias strength of the PUF circuit is below a threshold, and wherein the PUF circuit is forced to a pre-determined value or not used to generate an encryption code based on being marked as a dark bit.

10. The PUF circuit of claim 1, wherein, during a bit generation process of the PUF circuit, the first and second pre-charge transistors are turned on and then off, responsive to the clock signal, to generate an output bit, wherein the PUF circuit is to perform multiple instances of the bit generation process to generate respective output bits, and wherein the PUF circuit further comprises:

a counter coupled to the bit node to count a number of the instances of the bit generation process for which the PUF circuit generates an output bit with a first logic value, wherein a value of the PUF bit associated with the PUF circuit is based on the counted number.

11. The PUF circuit of claim 1, wherein the first and second clock paths include a first metal layer that is coupled to a clock terminal to receive the clock signal, and wherein the bit node and the bit bar node are disposed in a second metal layer that is below the first metal layer.

12. The PUF circuit of claim 11, wherein the first and second clock paths are symmetrical.

13. A physically unclonable function (PUF) circuit comprising:

a bit node and a bit bar node;

a first inverter and a second inverter that are cross-coupled between the bit node and the bit bar node;

a first pre-charge transistor coupled between the bit node and a power supply rail;

a second pre-charge transistor coupled between the bit bar node and the power supply rail, the first and second pre-charge transistors to receive a clock signal via respective first and second clock paths;

a programmable delay chain disposed on the first clock path; and

mask generation circuitry coupled to the programmable delay chain to;

control the programmable delay chain to provide a series of different delay values on the first clock path, wherein the PUF circuit is to generate respective output bits associated with individual delay values of the series of delay values; and

determine a bias strength of the PUF circuit based on the output bits.

14. The PUF circuit of claim 13, wherein the programmable delay chain is a first programmable delay chain, wherein the PUF circuit further includes a second programmable delay chain disposed on the second clock path, and wherein the mask generation circuitry is further to control the second programmable delay chain to provide a series of different delay values on the second clock path, wherein the PUF circuit is to generate respective output bits associated with individual delay values of the series of delay values on the second clock path.

15. The PUF circuit of claim 13, wherein the mask generation circuitry is to mark the PUF circuit as a dark bit if the determined bias strength of the PUF circuit is below a threshold, and wherein the PUF circuit is forced to a pre-determined value or not used to generate an encryption code based on being marked as a dark bit.

16. The PUF circuit of claim 13, wherein the bit node, the bit bar node, the first and second inverters, the first and second pre-charge transistors, and the programmable delay chain are included in a first PUF cell, and wherein the mask generation circuitry is to determine the bias strength for an array of PUF cells to generate a dark bit mask.

17. The PUF circuit of claim 13, wherein the first and second clock paths include a first metal layer that is coupled to a clock terminal to receive the clock signal, wherein the first and second clock paths are symmetrical, and wherein the bit node and the bit bar node are disposed in a second metal layer that is below the first metal layer.

18. An apparatus comprising:

a clock terminal to receive a clock signal;

a physically unclonable function (PUF) cell coupled to the clock terminal to receive the clock signal, the PUF cell to perform multiple instances of a bit generation process, responsive to the clock signal, to generate respective output bits at a bit node of the PUF cell;

a counter coupled to the bit node to count a number of instances for which the output bit has a first logic value; and

processing circuitry coupled to the bit node, the processing circuitry to;

determine that a value of a PUF bit associated with the PUF cell is the first logic value if the counted number is above a first threshold;

determine that the value of the PUF bit is a second logic value if the counted number is below a second threshold that is less than the first threshold; and

mark the PUF bit as a dark bit if the counted number is between the first and second thresholds.

19. The apparatus of claim 18, wherein the PUF cell further includes:

a bit bar node;

a first inverter and a second inverter that are cross-coupled between the bit node and the bit bar node;

a first pre-charge transistor coupled to the bit node and to charge the bit node responsive to the clock signal; and

a second pre-charge transistor coupled to the bit bar node to charge the bit bar node responsive to the clock signal.

20. The apparatus of claim 19, wherein the PUF cell further comprises:

a first delay chain disposed on a first clock path between the clock terminal and the first pre-charge transistor;

a second delay chain disposed on a second clock path between the clock terminal and the second pre-charge transistor; and

control circuitry to;

if the processing circuitry determines that the value of the PUF bit is the first logic value, write the second logic value to the bit node during a delay hardening mode of the PUF cell to provide a differential delay between the first and second clock paths; and

if the processing circuitry determines that the value of the PUF bit is the second logic value, write the first logic value to the bit node during the delay hardening mode of the PUF cell to provide a differential delay between the first and second clock paths.

21. The apparatus of claim 20, wherein the PUF cell further comprises:

an enable terminal to receive an enable signal to switch the PUF cell between a bit generation mode and the delay hardening mode;

a first negative-AND (NAND) gate having a first input terminal coupled to the clock terminal to receive the clock signal, a second input terminal coupled to the enable terminal to receive the enable signal, and an output terminal;

a second NAND gate having a first input terminal coupled to receive an inverse of the enable signal, a second input terminal coupled to an output terminal of a flip-flop to receive an output signal, and an output terminal; and

a third NAND gate having a first input terminal coupled to the output terminal of the first NAND gate, a second input terminal coupled to the output terminal of the second NAND gate, and an output terminal coupled to the first delay chain.

22. The apparatus of claim 21, wherein the PUF cell further comprises:

a fourth NAND gate having a first input terminal coupled to receive an inverse of the enable signal, a second input terminal coupled to an output bar terminal of the flip-flop to receive an output bar signal, and an output terminal; and

a fifth NAND gate having a first input terminal coupled to the output terminal of the first NAND gate, a second input terminal coupled to the output terminal of the fourth NAND gate, and an output terminal coupled to the second delay chain.

23. The apparatus of claim 19, wherein the first pre-charge transistor is coupled to the clock terminal via a first clock path, wherein the second pre-charge transistor is coupled to the clock terminal via a second clock path, wherein the first and second clock paths are symmetrical and include a first metal layer, and wherein the bit node and the bit bar node are disposed in a second metal layer that is below the first metal layer.

24. The apparatus of claim 18, wherein the PUF cell is a first PUF cell of an array of PUF cells, and wherein the processing circuitry is to determine the values for PUF bits associated with the array of PUF cells to generate an encryption code.

25. The apparatus of claim 24, wherein the clock terminal, the array of PUF cells, the counter, and the processing circuitry are included in an integrated circuit, and wherein the apparatus further includes a display and a memory coupled to the integrated circuit.