Printed circuit board, design method thereof and mainboard of terminal product

• US 9,519,308 B2
• Filed: 03/07/2014
• Issued: 12/13/2016
• Est. Priority Date: 03/23/2007
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Shen, Xiaolan, Ye, Qingsong, Wei, Konggang
• Primary Examiner(s): Sawyer, Steven T
• Application Number:
  US14/200,642
• Publication Number:
  US 20140185217A1
• Time in Patent Office: 1,012 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/16 Constructional details or arrangements
• CPC Class Codes: H05K 1/0218 by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 1/025 Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance H05K1/024 and H05K1/0243 take precedence; for semiconductor devices H01L23/66
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/116 Lands, clearance holes or other lay-out details concerning the surrounding of a via
• CPC Class Codes: H05K 2201/0191 wherein the thickness of the dielectric plays an important role
• CPC Class Codes: H05K 2201/0715 provided by an outer layer of PCB
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/09627 Special connections between adjacent vias, not for grounding vias

Abstract

A printed circuit board and a design method thereof are disclosed. The design method includes: wiring signal lines on an area basis at inner layers adjacent to outer surface layers; arranging the outer surface layers with no wiring or few wirings and interconnecting the outer surface layers through vias, so that the outer surface layers function as a primary ground; and setting parameters of a line width and a layer height to control a target impedance value. The printed circuit board includes outer surface layers and two inner layers therebetween. The inner layers adjacent to the outer surface layers are used for arranging signal lines on an area basis; and the outer surface layers are arranged with no wiring or few wirings and are interconnected as a primary ground through vias. The invention also discloses a mainboard of a terminal product using the printed circuit board.

Claims

1. A printed circuit board, comprising outer surface layers and at least two inner layers between the outer surface layers, wherein:

signal lines are arranged on an area basis on the at least two inner layers;

each of the outer surface layers of the printed circuit board is arranged with a metal sheet, wherein each of the outer surface layers is disposed on an outer surface of the printed circuit board;

the outer surface layers are interconnected by at least one through via, so that the outer surface layers function as a primary ground;

the printed circuit board does not include a ground plane at any of the at least two inner layers;

an interlayer distance between two adjacent inner layers is at least twice a distance from each of the two adjacent inner layers to a corresponding one of the outer surface layers closest to an inner layer;

the printed circuit board comprises at least three base plates and the outer surface layers and the at least two inner layers are formed on surfaces of the base plates; and

a number of layers of the at least two inner layers in the printed circuit board is two, and at least one BGA-packaged device is provide on the printed circuit board, a blind via in a BGD area is arranged below a pad of the BGA-packaged device, and a ground copper sheet with a large area in the BGA area is a mesh copper sheet.

2. The printed circuit board according to claim 1, wherein:

one of the outer surface layers is a keyboard arrangement side, and an inner layer adjacent to the keyboard arrangement side is used for arranging radio frequency signal lines, power signal lines, clock signal lines and audio signal lines.

3. The printed circuit board according to claim 1, wherein:

one of the outer surface layers is a device arrangement side, the inner layer adjacent to the device arrangement side is used for arranging radio frequency signal lines, data buses and multimedia signal lines.

4. A mainboard of a terminal product, comprising a basedband or radio frequency core chip, wherein:

the mainboard of the terminal product is a four-layer printed circuit board comprising surface layers and two inner layers between the surface layers;

the surface layers comprise a top layer and a bottom layer, the top layer is configured as a primary reference ground layer consisting of a ground copper sheet with a large area, the bottom layer is interconnected with the top layer by through vias, and the inner layers are primary wiring layers where wiring areas are divided by functions;

a distance between the inner layers is at least twice a distance between each of the surface layers and the inner layers adjacent to the surface layer;

the wiring area at each of the inner layers corresponds to the ground copper sheet with the large area at a layer adjacent to the inner layer or vertically arranged traveling lines at the layer adjacent to the inner layer; and

a blank area at the inner layers other than the wiring areas is grounded, the top layer is arranged as a keyboard arrangement side of the terminal product, the bottom layer is arranged as a primary device arrangement side of the terminal device, and audio lines are arranged at the inner layer adjacent to the top layer, and correspond to the keyboard arrangement side and avoid a projection of a keyboard pad at the inner layer adjacent to the top layer.

5. The mainboard according to claim 4, wherein devices internal to each functional module are arranged in a traveling direction of a circuit signal, and a radio frequency area and a digital area are arranged respectively within a shielding structure.

6. The mainboard according to claim 5, wherein for impedance of a radio frequency wiring at least one of the following are controlled so as to control the continuity of the impedance of the radio frequency wiring indirectly:

a consistency of a line width, an interlayer distance, a dielectric DK value and/or a copper thickness.

7. The mainboard according to claim 4, wherein the surface layers of the mainboard of the terminal product are arranged with wirings disposed within a shielding structure.

8. The mainboard according to claim 4, wherein master power lines are arranged along an outer edge of the inner layers of the mainboard and isolated from the board edge by a ground line.

9. The mainboard according to claim 4, wherein audio lines are arranged at an inner layer adjacent to the bottom layer and avoid projections of device pin pads of high speed signals at the inner layer adjacent to the bottom layer and power signals at the primary device arrangement side.

10. The mainboard according to claim 4, wherein audio lines are isolated from surrounding signal lines at the same layer by a ground line.

11. The mainboard according to claim 4, wherein clock lines are arranged at the inner layer adjacent to the bottom layer and avoid projections of device pin pads of high speed signals and power signals at the inner layer adjacent to the bottom layer and power signals at the primary device arrangement side.

12. The mainboard according to claim 4, wherein data lines are arranged at the inner layer adjacent to the primary device arrangement side, and include by categories LCD data lines, interface lines, JTAG lines, serial port lines, UIM card lines and keyboard lines;

the data lines are clustered by categories and are wired by clusters, and the clusters are isolated from each other by a ground line.

13. The mainboard according to claim 4, wherein the mainboard has a 1+2+1 laminated structure including an interposed double sided board, two sides of which are laminated respectively with a prepreg and a copper foil.

14. The mainboard according to claim 13, wherein the mainboard of the terminal product is provided with at least one BGA-packaged device with a pin pitch selected from any or combination of 1 mm, 0.8 mm, 0.65 mm, 0.5 mm and 0.4 mm.

15. The mainboard according to claim 13, wherein thicknesses between the surface layers and respective adjacent inner layers range from 60 μ

m to 80 μ

m.

16. The mainboard according to claim 13, wherein a thickness of a dielectric between the inner layers is above or equal to 0.1 mm and the total thickness of the mainboard is below or equal to 1.6 mm.

17. The mainboard according to claim 4, wherein the mainboard has a 2+2 laminated structure including two double side boards separated by a prepreg layer.

18. The mainboard according to claim 17, wherein the mainboard of the terminal product is provided with at least one BGA-packaged device, the laser blind via in a BGA area is provided below a pad of the BGA-packaged device, and the ground copper sheet with the large area in the BGA area is a mesh copper sheet.

19. The mainboard according to claim 17, wherein a distance between the surface layers and the respective adjacent inner layers is above or equal to 0.1 mm.

20. The mainboard according to claim 17, wherein the total board thickness of the mainboard is below or equal to 2 mm.