Multi-array operation support and related devices, systems and software

• US 9,519,578 B1
• Filed: 11/25/2015
• Issued: 12/13/2016
• Est. Priority Date: 01/28/2013
• Status: Active Grant

• Current Assignee: Radian Memory Systems, LLC
• Original Assignee: Radian Memory Systems, Inc.
• Inventors: Kuzmin, Andrey V., Wayda, James G.
• Primary Examiner(s): Bataille, Pierre-Michel
• Application Number:
  US14/951,708
• Time in Patent Office: 384 Days
• Field of Search: 711/103, 711/170, 711/114, 711/202, 711/203, 711/154
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 16/1847 specifically adapted to static storage, e.g. adapted to flash memory or SSD
• CPC Class Codes: G06F 2015/766 Flash EPROM
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories

Abstract

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Claims

1. A flash memory controller integrated circuit to receive memory access requests from a host, the flash memory controller integrated circuit comprising:

at least one host interface to receive the memory access requests from the host and to exchange data with the host;

at least one memory interface to program the data into the flash memory dies, and to read the data therefrom;

circuitry to map, for each memory access request, a logical base address conveyed by the memory access request to a variable number of physical locations in respective ones of the flash memory dies, depending on logical base address, such that

a first logical base address is mapped to a first number of the physical locations,

a second logical base address is mapped to a second number of the physical locations,

wherein the first number and the second number are different, and are each one or more; and

circuitry to control data programming and read operations in the flash memory dies via the memory interface in response to the memory access requests, according to the mapped, variable number of physical locations;

wherein the physical locations are respective ones of a unit of flash memory cells, such that a variable data size is to be exchanged between the flash memory controller integrated circuit and the host in association with each memory access request, corresponding to the logical base address conveyed with the memory access request.

2. The flash memory controller integrated circuit of claim 1, further comprising:

circuitry to track page release status of each of the physical locations in each of the flash memory dies;

circuitry to receive deallocate commands respectively directed to the first logical base address and to the second logical base address; and

circuitry to update, responsive to receipt of the deallocate commands, page release data for each of the first number of physical locations and for each of the second number of physical locations, dependent on whether a given deallocate command is directed to the first logical base address or the second logical base address.

3. The flash memory controller integrated circuit of claim 1, wherein the circuitry to map is to perform address translation for each one of a variable number of the flash memory dies, the variable number dependent on whether a given command is directed to the first logical base address or the second logical base address.

4. The flash memory controller integrated circuit of claim 1, wherein the circuitry to map is to translate a logical base address to both of a first physical address in a first one of the memory dies and a second physical address in a second one of the memory dies, the first and second physical addresses being independent of each other.

5. The flash memory controller integrated circuit of claim 1, wherein the flash memory dies comprise a first flash memory die and a second flash memory die, and wherein:

the at least one memory interface to program the data into the flash memory dies, and to read the data therefrom, comprises a first memory interface to program the data into the first flash memory die via a first channel, and a second memory interface to program the data into a second flash memory die via a second channel; and

the first logical base address is to be mapped to at least one physical location in the first flash memory die and no physical locations in the second flash memory die.

6. The flash memory controller integrated circuit of claim 1, wherein the flash memory dies comprise a first flash memory die and a second flash memory die, and wherein:

the at least one memory interface to program the data into the flash memory dies, and to read the data therefrom, comprises a first memory interface to program the data into the first flash memory die via a first channel, and a second memory interface to program the data into a second flash memory die via a second channel; and

the second logical base address is to be mapped to at least one physical location in the first flash memory die and at least one physical location in the second flash memory die.

7. The flash memory controller integrated circuit of claim 1, wherein the flash memory dies include first and second flash memory dies, wherein the first logical base address is to be mapped to at least one physical location in each of the first and second flash memory dies, and wherein the memory controller integrated circuit further comprises circuitry to perform garbage collection in the first flash memory die and garbage collection in the second flash memory die.

8. The flash memory controller integrated circuit of claim 1, wherein the memory access requests include a write transaction, wherein data segments are to be programmed into respective ones of the flash memory dies, wherein the flash memory controller integrated circuit further comprises circuitry to monitor completion of programming the data segments into the respective ones of the flash memory dies, and further, to transmits an indication to the host via the at least one host interface to inform the host of the completion.

9. A memory device, comprising:

memory dies; and

a flash memory controller integrated circuit to receive memory access requests from a host, wherein the flash memory controller integrated circuit further comprises

at least one host interface to receive the memory access requests from the host and to exchange data with the host,

at least one memory interface to program the data into the flash memory dies, and to read the data therefrom,

circuitry to map, for each memory access request, a logical base address conveyed by the memory access request to a variable number of physical locations in respective ones of the flash memory dies, depending on logical base address, such that

a first logical base address is mapped to a first number of the physical locations,

a second logical base address is mapped to a second number of the physical locations,

wherein the first number and the second number are different, and are each one or more, and

circuitry to control data programming and read operations in the flash memory dies via the memory interface in response to the memory access requests, according to the mapped, variable number of physical locations;

wherein the physical locations are respective ones of a unit of flash memory cells, such that a variable data size is to be exchanged between the flash memory controller integrated circuit and the host in association with each memory access request, corresponding to the logical base address conveyed with the memory access request.

10. The memory device of claim 9, wherein the flash memory controller integrated circuit further comprises:

circuitry to track page release status of each of the physical locations in each of the flash memory dies;

circuitry to receive deallocate commands respectively directed to the first logical base address and to the second logical base address;

circuitry to update, in response to receipt of the deallocate commands, page release data for each of the first number of physical locations and for each of the second number of physical locations, dependent on whether a given deallocate command is directed to the first logical base address or the second logical base address.

11. The memory device of claim 9, wherein the circuitry to map is to perform address translation for each one of a variable number of the flash memory dies, the variable number dependent on whether a given command is directed to the first logical base address or the second logical base address.

12. The memory device of claim 9, wherein the circuitry to map is to translate a logical base address to both of a first physical address in a first one of the memory dies and a second physical address in a second one of the memory dies, the first and second physical addresses being independent of each other.

13. The memory device of claim 9, wherein:

the flash memory dies comprise a first flash memory die and a second flash memory die;

the at least one memory interface to program the data into the flash memory dies, and to read the data therefrom, comprises a first memory interface to program the data into the first flash memory die via a first channel, and a second memory interface to program the data into a second flash memory die via a second channel; and

the first logical base address is to be mapped to at least one physical location in the first flash memory die and no physical locations in the second flash memory die.

14. The memory device of claim 9, wherein:

the flash memory dies comprise a first flash memory die and a second flash memory die;

the at least one memory interface to program the data into the flash memory dies, and to read the data therefrom, comprises a first memory interface to program the data into the first flash memory die via a first channel, and a second memory interface to program the data into a second flash memory die via a second channel; and

the second logical base address is to be mapped to at least one physical location in the first flash memory die and at least one physical location in the second flash memory die.

15. The memory device of claim 9, wherein the flash memory dies include first and second flash memory dies, wherein the first logical base address is to be mapped to at least one physical location in each of the first and second flash memory dies, and wherein the memory controller integrated circuit further comprises circuitry to perform garbage collection in the first flash memory die and garbage collection in the second flash memory die.

16. The memory device of claim 9, wherein the memory access requests include a write transaction, wherein data segments are to be programmed into respective ones of the flash memory dies, wherein the flash memory controller integrated circuit further comprises circuitry to monitor completion of programming the data segments into the respective ones of the flash memory dies, and further, to transmit an indication to the host via the at least one host interface to inform the host of the completion.

17. The memory device of claim 9, embodied as a solid state drive.

18. A method of operating flash memory, wherein the flash memory comprises flash memory dies, and wherein the method comprises causing a flash memory controller integrated circuit to:

receive memory access requests from a host via at least one host interface, and exchange data with the host via the at least one host interface;

map, for each memory access request, a logical base address conveyed by the memory access request to a variable number of physical locations in respective ones of the flash memory dies, depending on logical base address, such that

a first logical base address is mapped to a first number of the physical locations,

a second logical base address is mapped to a second number of the physical locations,

wherein the first number and the second number are different, and are each one or more; and

control data programming and read operations in the flash memory dies via the memory interface in response to the memory access requests, according to the mapped, variable number of physical locations;

wherein the physical locations are respective ones of a unit of flash memory cells, such that a variable data size is to be exchanged between the flash memory controller integrated circuit and the host in association with each memory access request, corresponding to the logical base address conveyed with the memory access request.

19. The method of claim 18, further comprising causing the flash memory controller integrated circuit to:

track page release status of each physical location in each of the flash memory dies;

receive deallocate commands respectively directed to the first logical base address and to the second logical base address; and

update, responsive to receipt of the deallocate commands, page release data for each of the first number of physical locations and for each of the second number of physical locations, dependent on whether a given deallocate command is directed to the first logical base address or the second logical base address.

20. The method of claim 18, further comprising causing the flash memory controller integrated circuit to perform address translation for each one of a variable number of the flash memory dies, the variable number dependent on whether a given command is directed to the first logical base address or the second logical base address.

21. The method of claim 18, wherein causing the flash memory controller integrated circuit to map comprises causing the flash memory controller integrated circuit to translate a logical base address to both of a first physical address in a first one of the memory dies and a second physical address in a second one of the memory dies, the first and second physical addresses being independent of each other.

22. The method of claim 21, further comprising causing the flash memory controller integrated circuit to perform garbage collection for the first flash memory die, and causing the flash memory controller integrated circuit to perform garbage collection for the second flash memory die.

23. The method of claim 18, wherein the memory access requests include a write transaction, and wherein the method further comprises writing data segments corresponding to the write transaction into respective ones of the flash memory dies, monitoring completion of writing the data segments into the respective ones of the flash memory dies, and further, transmitting in indication to the host via the at least one host interface to inform the host of the completion.